JAJSE27 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-41 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-42 100Base-TX Transmit Timing
          3. Table 5-43 10Base-T Normal Link Pulse Timing
          4. Table 5-44 Auto-Negotiation Fast Link Pulse (FLP) Timing
          5. Table 5-45 100Base-TX Signal Detect Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-46 ULPI Interface Timing
      16. 5.15.16 Analog Comparator
        1. Table 5-47 Analog Comparator Characteristics
        2. Table 5-48 Analog Comparator Characteristics
        3. Table 5-49 Analog Comparator Voltage Reference Characteristics
        4. Table 5-50 Analog Comparator Voltage Reference Characteristics
      17. 5.15.17 Pulse-Width Modulator (PWM)
        1. Table 5-51 PWM Timing Characteristics
      18. 5.15.18 Emulation and Debug
        1. Table 5-52 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

4.2 Pin Attributes

Table 4-1 lists GPIO pins with special considerations. Most GPIO pins are configured as GPIOs and are high-impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and GPIOPCTL = 0). Special consideration pins may be programed to a non-GPIO function or may have special commit controls out of reset. In addition, a POR returns these GPIOs to their original special consideration state.

Table 4-1 GPIO Pins With Special Considerations

GPIO PINSDEFAULT RESET STATEGPIOAFSELGPIODENGPIOPDRGPIOPURGPIOPCTLGPIOCR
PC[3:0] JTAG/SWD 1 1 0 1 0x1 0
PD[7] GPIO(1) 0 0 0 0 0x0 0
PE[7] GPIO(1) 0 0 0 0 0x0 0
(1) This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.

Table 4-2 describes the pin attributes.

Table 4-2 Pin Attributes

PIN NUMBERSIGNAL NAME SIGNAL TYPE(1)BUFFER TYPE(2)PIN MUX ENCODING POWER SOURCE(3)STATE AFTER RESET RELEASE(4)
1 PD0 I/O LVCMOS – VDD OFF
AIN15 I Analog PD0 N/A
C0o O LVCMOS PD0 (5) N/A
I2C7SCL I/O LVCMOS PD0 (2) N/A
SSI2XDAT1 I/O LVCMOS PD0 (15) N/A
T0CCP0 I/O LVCMOS PD0 (3) N/A
2 PD1 I/O LVCMOS – VDD OFF
AIN14 I Analog PD1 N/A
C1o O LVCMOS PD1 (5) N/A
I2C7SDA I/O LVCMOS PD1 (2) N/A
SSI2XDAT0 I/O LVCMOS PD1 (15) N/A
T0CCP1 I/O LVCMOS PD1 (3) N/A
3 PD2 I/O LVCMOS – VDD OFF
AIN13 I Analog PD2 N/A
C2o O LVCMOS PD2 (5) N/A
I2C8SCL I/O LVCMOS PD2 (2) N/A
SSI2Fss I/O LVCMOS PD2 (15) N/A
T1CCP0 I/O LVCMOS PD2 (3) N/A
4 PD3 I/O LVCMOS – VDD OFF
AIN12 I Analog PD3 N/A
I2C8SDA I/O LVCMOS PD3 (2) N/A
SSI2Clk I/O LVCMOS PD3 (15) N/A
T1CCP1 I/O LVCMOS PD3 (3) N/A
5 PQ0 I/O LVCMOS – VDD OFF
EPI0S20 I/O LVCMOS PQ0 (15) N/A
SSI3Clk I/O LVCMOS PQ0 (14) N/A
6 PQ1 I/O LVCMOS – VDD OFF
EPI0S21 I/O LVCMOS PQ1 (15) N/A
SSI3Fss I/O LVCMOS PQ1 (14) N/A
7 VDD – Power Fixed N/A N/A
8 VDDA – Power Fixed N/A N/A
9 VREFA+ – Analog Fixed N/A N/A
10 GNDA – Power Fixed N/A N/A
11 PQ2 I/O LVCMOS – VDD OFF
EPI0S22 I/O LVCMOS PQ2 (15) N/A
SSI3XDAT0 I/O LVCMOS PQ2 (14) N/A
12 PE3 I/O LVCMOS – VDD OFF
AIN0 I Analog PE3 N/A
U1DTR O LVCMOS PE3 (1) N/A
13 PE2 I/O LVCMOS – VDD OFF
AIN1 I Analog PE2 N/A
U1DCD I LVCMOS PE2 (1) N/A
14 PE1 I/O LVCMOS – VDD OFF
AIN2 I Analog PE1 N/A
U1DSR I LVCMOS PE1 (1) N/A
15 PE0 I/O LVCMOS – VDD OFF
AIN3 I Analog PE0 N/A
U1RTS O LVCMOS PE0 (1) N/A
16 VDD – Power Fixed N/A N/A
17 GND – Power Fixed N/A N/A
18 PK0 I/O LVCMOS – VDD OFF
AIN16 I Analog PK0 N/A
EPI0S0 I/O LVCMOS PK0 (15) N/A
U4Rx I LVCMOS PK0 (1) N/A
19 PK1 I/O LVCMOS – VDD OFF
AIN17 I Analog PK1 N/A
EPI0S1 I/O LVCMOS PK1 (15) N/A
U4Tx O LVCMOS PK1 (1) N/A
20 PK2 I/O LVCMOS – VDD OFF
AIN18 I Analog PK2 N/A
EPI0S2 I/O LVCMOS PK2 (15) N/A
U4RTS O LVCMOS PK2 (1) N/A
21 PK3 I/O LVCMOS – VDD OFF
AIN19 I Analog PK3 N/A
EPI0S3 I/O LVCMOS PK3 (15) N/A
U4CTS I LVCMOS PK3 (1) N/A
22 PC7 I/O LVCMOS – VDD OFF
C0- I Analog PC7 N/A
EPI0S4 I/O LVCMOS PC7 (15) N/A
U5Tx O LVCMOS PC7 (1) N/A
23 PC6 I/O LVCMOS – VDD OFF
C0+ I Analog PC6 N/A
EPI0S5 I/O LVCMOS PC6 (15) N/A
U5Rx I LVCMOS PC6 (1) N/A
24 PC5 I/O LVCMOS – VDD OFF
C1+ I Analog PC5 N/A
EPI0S6 I/O LVCMOS PC5 (15) N/A
RTCCLK O LVCMOS PC5 (7) N/A
U7Tx O LVCMOS PC5 (1) N/A
25 PC4 I/O LVCMOS – VDD OFF
C1- I Analog PC4 N/A
EPI0S7 I/O LVCMOS PC4 (15) N/A
U7Rx I LVCMOS PC4 (1) N/A
26 VDD – Power Fixed N/A N/A
27 PQ3 I/O LVCMOS – VDD OFF
EPI0S23 I/O LVCMOS PQ3 (15) N/A
SSI3XDAT1 I/O LVCMOS PQ3 (14) N/A
28 VDD – Power Fixed N/A N/A
29 PH0 I/O LVCMOS – VDD OFF
EPI0S0 I/O LVCMOS PH0 (15) N/A
U0RTS O LVCMOS PH0 (1) N/A
30 PH1 I/O LVCMOS – VDD OFF
EPI0S1 I/O LVCMOS PH1 (15) N/A
U0CTS I LVCMOS PH1 (1) N/A
31 PH2 I/O LVCMOS – VDD OFF
EPI0S2 I/O LVCMOS PH2 (15) N/A
U0DCD I LVCMOS PH2 (1) N/A
32 PH3 I/O LVCMOS – VDD OFF
EPI0S3 I/O LVCMOS PH3 (15) N/A
U0DSR I LVCMOS PH3 (1) N/A
33 PA0 I/O LVCMOS – VDD OFF
CAN0Rx I LVCMOS PA0 (7) N/A
I2C9SCL I/O LVCMOS PA0 (2) N/A
T0CCP0 I/O LVCMOS PA0 (3) N/A
U0Rx I LVCMOS PA0 (1) N/A
34 PA1 I/O LVCMOS – VDD OFF
CAN0Tx O LVCMOS PA1 (7) N/A
I2C9SDA I/O LVCMOS PA1 (2) N/A
T0CCP1 I/O LVCMOS PA1 (3) N/A
U0Tx O LVCMOS PA1 (1) N/A
35 PA2 I/O LVCMOS – VDD OFF
I2C8SCL I/O LVCMOS PA2 (2) N/A
SSI0Clk I/O LVCMOS PA2 (15) N/A
T1CCP0 I/O LVCMOS PA2 (3) N/A
U4Rx I LVCMOS PA2 (1) N/A
36 PA3 I/O LVCMOS – VDD OFF
I2C8SDA I/O LVCMOS PA3 (2) N/A
SSI0Fss I/O LVCMOS PA3 (15) N/A
T1CCP1 I/O LVCMOS PA3 (3) N/A
U4Tx O LVCMOS PA3 (1) N/A
37 PA4 I/O LVCMOS – VDD OFF
I2C7SCL I/O LVCMOS PA4 (2) N/A
SSI0XDAT0 I/O LVCMOS PA4 (15) N/A
T2CCP0 I/O LVCMOS PA4 (3) N/A
U3Rx I LVCMOS PA4 (1) N/A
38 PA5 I/O LVCMOS – VDD OFF
I2C7SDA I/O LVCMOS PA5 (2) N/A
SSI0XDAT1 I/O LVCMOS PA5 (15) N/A
T2CCP1 I/O LVCMOS PA5 (3) N/A
U3Tx O LVCMOS PA5 (1) N/A
39 VDD – Power Fixed N/A N/A
40 PA6 I/O LVCMOS – VDD OFF
EPI0S8 I/O LVCMOS PA6 (15) N/A
I2C6SCL I/O LVCMOS PA6 (2) N/A
SSI0XDAT2 I/O LVCMOS PA6 (13) N/A
T3CCP0 I/O LVCMOS PA6 (3) N/A
U2Rx I LVCMOS PA6 (1) N/A
USB0EPEN O LVCMOS PA6 (5) N/A
41 PA7 I/O LVCMOS – VDD OFF
EPI0S9 I/O LVCMOS PA7 (15) N/A
I2C6SDA I/O LVCMOS PA7 (2) N/A
SSI0XDAT3 I/O LVCMOS PA7 (13) N/A
T3CCP1 I/O LVCMOS PA7 (3) N/A
U2Tx O LVCMOS PA7 (1) N/A
USB0EPEN O LVCMOS PA7 (11) N/A
USB0PFLT I LVCMOS PA7 (5) N/A
42 PF0 I/O LVCMOS – VDD OFF
EN0LED0 O LVCMOS PF0 (5) N/A
M0PWM0 O LVCMOS PF0 (6) N/A
SSI3XDAT1 I/O LVCMOS PF0 (14) N/A
TRD2 O LVCMOS PF0 (15) N/A
43 PF1 I/O LVCMOS – VDD OFF
EN0LED2 O LVCMOS PF1 (5) N/A
M0PWM1 O LVCMOS PF1 (6) N/A
SSI3XDAT0 I/O LVCMOS PF1 (14) N/A
TRD1 O LVCMOS PF1 (15) N/A
44 PF2 I/O LVCMOS – VDD OFF
M0PWM2 O LVCMOS PF2 (6) N/A
SSI3Fss I/O LVCMOS PF2 (14) N/A
TRD0 O LVCMOS PF2 (15) N/A
45 PF3 I/O LVCMOS – VDD OFF
M0PWM3 O LVCMOS PF3 (6) N/A
SSI3Clk I/O LVCMOS PF3 (14) N/A
TRCLK O LVCMOS PF3 (15) N/A
46 PF4 I/O LVCMOS – VDD OFF
EN0LED1 O LVCMOS PF4 (5) N/A
M0FAULT0 I LVCMOS PF4 (6) N/A
SSI3XDAT2 I/O LVCMOS PF4 (14) N/A
TRD3 O LVCMOS PF4 (15) N/A
47 VDD – Power Fixed N/A N/A
48 GND – Power Fixed N/A N/A
49 PG0 I/O LVCMOS – VDD OFF
EN0PPS O LVCMOS PG0 (5) N/A
EPI0S11 I/O LVCMOS PG0 (15) N/A
I2C1SCL I/O LVCMOS PG0 (2) N/A
M0PWM4 O LVCMOS PG0 (6) N/A
50 PG1 I/O LVCMOS – VDD OFF
EPI0S10 I/O LVCMOS PG1 (15) N/A
I2C1SDA I/O LVCMOS PG1 (2) N/A
M0PWM5 O LVCMOS PG1 (6) N/A
51 VDD – Power Fixed N/A N/A
52 VDD – Power Fixed N/A N/A
53 EN0RXIN I/O LVCMOS Fixed VDD N/A
54 EN0RXIP I/O LVCMOS Fixed VDD N/A
55 GND – Power Fixed N/A N/A
56 EN0TXON I/O LVCMOS Fixed VDD N/A
57 EN0TXOP I/O LVCMOS Fixed VDD N/A
58 GND – Power Fixed N/A N/A
59 RBIAS O Analog Fixed VDD N/A
60 PK7 I/O LVCMOS – VDD OFF
EPI0S24 I/O LVCMOS PK7 (15) N/A
I2C4SDA I/O LVCMOS PK7 (2) N/A
M0FAULT2 I LVCMOS PK7 (6) N/A
RTCCLK O LVCMOS PK7 (5) N/A
U0RI I LVCMOS PK7 (1) N/A
61 PK6 I/O LVCMOS – VDD OFF
EN0LED1 O LVCMOS PK6 (5) N/A
EPI0S25 I/O LVCMOS PK6 (15) N/A
I2C4SCL I/O LVCMOS PK6 (2) N/A
M0FAULT1 I LVCMOS PK6 (6) N/A
62 PK5 I/O LVCMOS – VDD OFF
EN0LED2 O LVCMOS PK5 (5) N/A
EPI0S31 I/O LVCMOS PK5 (15) N/A
I2C3SDA I/O LVCMOS PK5 (2) N/A
M0PWM7 O LVCMOS PK5 (6) N/A
63 PK4 I/O LVCMOS – VDD OFF
EN0LED0 O LVCMOS PK4 (5) N/A
EPI0S32 I/O LVCMOS PK4 (15) N/A
I2C3SCL I/O LVCMOS PK4 (2) N/A
M0PWM6 O LVCMOS PK4 (6) N/A
64 WAKE I LVCMOS Fixed VBAT N/A
65 HIB O LVCMOS Fixed VBAT N/A
66 XOSC0 I Analog Fixed VBAT N/A
67 XOSC1 O Analog Fixed VBAT N/A
68 VBAT – Power Fixed N/A N/A
69 VDD – Power Fixed N/A N/A
70 RST I LVCMOS Fixed VDD N/A
71 PM7 I/O LVCMOS – VDD OFF
T5CCP1 I/O LVCMOS PM7 (3) N/A
TMPR0 I/O LVCMOS PM7 N/A
U0RI I LVCMOS PM7 (1) N/A
72 PM6 I/O LVCMOS – VDD OFF
T5CCP0 I/O LVCMOS PM6 (3) N/A
TMPR1 I/O LVCMOS PM6 N/A
U0DSR I LVCMOS PM6 (1) N/A
73 PM5 I/O LVCMOS – VDD OFF
T4CCP1 I/O LVCMOS PM5 (3) N/A
TMPR2 I/O LVCMOS PM5 N/A
U0DCD I LVCMOS PM5 (1) N/A
74 PM4 I/O LVCMOS – VDD OFF
T4CCP0 I/O LVCMOS PM4 (3) N/A
TMPR3 I/O LVCMOS PM4 N/A
U0CTS I LVCMOS PM4 (1) N/A
75 PM3 I/O LVCMOS – VDD OFF
EPI0S12 I/O LVCMOS PM3 (15) N/A
T3CCP1 I/O LVCMOS PM3 (3) N/A
76 PM2 I/O LVCMOS – VDD OFF
EPI0S13 I/O LVCMOS PM2 (15) N/A
T3CCP0 I/O LVCMOS PM2 (3) N/A
77 PM1 I/O LVCMOS – VDD OFF
EPI0S14 I/O LVCMOS PM1 (15) N/A
T2CCP1 I/O LVCMOS PM1 (3) N/A
78 PM0 I/O LVCMOS – VDD OFF
EPI0S15 I/O LVCMOS PM0 (15) N/A
T2CCP0 I/O LVCMOS PM0 (3) N/A
79 VDD – Power Fixed N/A N/A
80 GND – Power Fixed N/A N/A
81 PL0 I/O LVCMOS – VDD OFF
EPI0S16 I/O LVCMOS PL0 (15) N/A
I2C2SDA I/O LVCMOS PL0 (2) N/A
M0FAULT3 I LVCMOS PL0 (6) N/A
USB0D0 I/O LVCMOS PL0 (14) N/A
82 PL1 I/O LVCMOS – VDD OFF
EPI0S17 I/O LVCMOS PL1 (15) N/A
I2C2SCL I/O LVCMOS PL1 (2) N/A
PhA0 I LVCMOS PL1 (6) N/A
USB0D1 I/O LVCMOS PL1 (14) N/A
83 PL2 I/O LVCMOS – VDD OFF
C0o O LVCMOS PL2 (5) N/A
EPI0S18 I/O LVCMOS PL2 (15) N/A
PhB0 I LVCMOS PL2 (6) N/A
USB0D2 I/O LVCMOS PL2 (14) N/A
84 PL3 I/O LVCMOS – VDD OFF
C1o O LVCMOS PL3 (5) N/A
EPI0S19 I/O LVCMOS PL3 (15) N/A
IDX0 I LVCMOS PL3 (6) N/A
USB0D3 I/O LVCMOS PL3 (14) N/A
85 PL4 I/O LVCMOS – VDD OFF
EPI0S26 I/O LVCMOS PL4 (15) N/A
T0CCP0 I/O LVCMOS PL4 (3) N/A
USB0D4 I/O LVCMOS PL4 (14) N/A
86 PL5 I/O LVCMOS – VDD OFF
EPI0S33 I/O LVCMOS PL5 (15) N/A
T0CCP1 I/O LVCMOS PL5 (3) N/A
USB0D5 I/O LVCMOS PL5 (14) N/A
87 VDDC – Power Fixed N/A N/A
88 OSC0 I Analog Fixed VDD N/A
89 OSC1 O Analog Fixed VDD N/A
90 VDD – Power Fixed N/A N/A
91 PB2 I/O LVCMOS – VDD OFF
EPI0S27 I/O LVCMOS PB2 (15) N/A
I2C0SCL I/O LVCMOS PB2 (2) N/A
T5CCP0 I/O LVCMOS PB2 (3) N/A
USB0STP O LVCMOS PB2 (14) N/A
92 PB3 I/O LVCMOS – VDD OFF
EPI0S28 I/O LVCMOS PB3 (15) N/A
I2C0SDA I/O LVCMOS PB3 (2) N/A
T5CCP1 I/O LVCMOS PB3 (3) N/A
USB0CLK O LVCMOS PB3 (14) N/A
93 PL7 I/O LVCMOS – VDD OFF
T1CCP1 I/O LVCMOS PL7 (3) N/A
USB0DM I/O Analog PL7 N/A
94 PL6 I/O LVCMOS – VDD OFF
T1CCP0 I/O LVCMOS PL6 (3) N/A
USB0DP I/O Analog PL6 N/A
95 PB0 I/O LVCMOS – VDD OFF
CAN1Rx I LVCMOS PB0 (7) N/A
I2C5SCL I/O LVCMOS PB0 (2) N/A
T4CCP0 I/O LVCMOS PB0 (3) N/A
U1Rx I LVCMOS PB0 (1) N/A
USB0ID I Analog PB0 N/A
96 PB1 I/O LVCMOS – VDD OFF
CAN1Tx O LVCMOS PB1 (7) N/A
I2C5SDA I/O LVCMOS PB1 (2) N/A
T4CCP1 I/O LVCMOS PB1 (3) N/A
U1Tx O LVCMOS PB1 (1) N/A
USB0VBUS I/O Analog PB1 N/A
97 PC3 I/O LVCMOS – VDD OFF
TDO/SWO O LVCMOS PC3 (1) PU
98 PC2 I/O LVCMOS – VDD N/A
TDI I LVCMOS PC2 (1) PU
99 PC1 I/O LVCMOS – VDD OFF
TMS/SWDIO I/O LVCMOS PC1 (1) PU
100 PC0 I/O LVCMOS – VDD OFF
TCK/SWCLK I LVCMOS PC0 (1) PU
101 VDD – Power Fixed N/A N/A
102 PQ4 I/O LVCMOS – VDD OFF
DIVSCLK O LVCMOS PQ4 (7) N/A
U1Rx I LVCMOS PQ4 (1) N/A
103 PP2 I/O LVCMOS – VDD OFF
EPI0S29 I/O LVCMOS PP2 (15) N/A
U0DTR O LVCMOS PP2 (1) N/A
USB0NXT O LVCMOS PP2 (14) N/A
104 PP3 I/O LVCMOS – VDD OFF
EPI0S30 I/O LVCMOS PP3 (15) N/A
RTCCLK O LVCMOS PP3 (7) N/A
U0DCD I LVCMOS PP3 (2) N/A
U1CTS I LVCMOS PP3 (1) N/A
USB0DIR O LVCMOS PP3 (14) N/A
105 PP4 I/O LVCMOS – VDD OFF
U0DSR I LVCMOS PP4 (2) N/A
U3RTS O LVCMOS PP4 (1) N/A
USB0D7 I/O LVCMOS PP4 (14) N/A
106 PP5 I/O LVCMOS – VDD OFF
I2C2SCL I/O LVCMOS PP5 (2) N/A
U3CTS I LVCMOS PP5 (1) N/A
USB0D6 I/O LVCMOS PP5 (14) N/A
107 PN0 I/O LVCMOS – VDD OFF
U1RTS O LVCMOS PN0 (1) N/A
108 PN1 I/O LVCMOS – VDD OFF
U1CTS I LVCMOS PN1 (1) N/A
109 PN2 I/O LVCMOS – VDD OFF
EPI0S29 I/O LVCMOS PN2 (15) N/A
U1DCD I LVCMOS PN2 (1) N/A
U2RTS O LVCMOS PN2 (2) N/A
110 PN3 I/O LVCMOS – VDD OFF
EPI0S30 I/O LVCMOS PN3 (15) N/A
U1DSR I LVCMOS PN3 (1) N/A
U2CTS I LVCMOS PN3 (2) N/A
111 PN4 I/O LVCMOS – VDD OFF
EPI0S34 I/O LVCMOS PN4 (15) N/A
I2C2SDA I/O LVCMOS PN4 (3) N/A
U1DTR O LVCMOS PN4 (1) N/A
U3RTS O LVCMOS PN4 (2) N/A
112 PN5 I/O LVCMOS – VDD OFF
EPI0S35 I/O LVCMOS PN5 (15) N/A
I2C2SCL I/O LVCMOS PN5 (3) N/A
U1RI I LVCMOS PN5 (1) N/A
U3CTS I LVCMOS PN5 (2) N/A
113 VDD – Power Fixed N/A N/A
114 GND – Power Fixed N/A N/A
115 VDDC – Power Fixed N/A N/A
116 PJ0 I/O LVCMOS – VDD OFF
EN0PPS O LVCMOS PJ0 (5) N/A
U3Rx I LVCMOS PJ0 (1) N/A
117 PJ1 I/O LVCMOS – VDD OFF
U3Tx O LVCMOS PJ1 (1) N/A
118 PP0 I/O LVCMOS – VDD OFF
C2+ I Analog PP0 N/A
SSI3XDAT2 I/O LVCMOS PP0 (15) N/A
U6Rx I LVCMOS PP0 (1) N/A
119 PP1 I/O LVCMOS – VDD OFF
C2- I Analog PP1 N/A
SSI3XDAT3 I/O LVCMOS PP1 (15) N/A
U6Tx O LVCMOS PP1 (1) N/A
120 PB5 I/O LVCMOS – VDD OFF
AIN11 I Analog PB5 N/A
I2C5SDA I/O LVCMOS PB5 (2) N/A
SSI1Clk I/O LVCMOS PB5 (15) N/A
U0RTS O LVCMOS PB5 (1) N/A
121 PB4 I/O LVCMOS – VDD OFF
AIN10 I Analog PB4 N/A
I2C5SCL I/O LVCMOS PB4 (2) N/A
SSI1Fss I/O LVCMOS PB4 (15) N/A
U0CTS I LVCMOS PB4 (1) N/A
122 VDD – Power Fixed N/A N/A
123 PE4 I/O LVCMOS – VDD OFF
AIN9 I Analog PE4 N/A
SSI1XDAT0 I/O LVCMOS PE4 (15) N/A
U1RI I LVCMOS PE4 (1) N/A
124 PE5 I/O LVCMOS – VDD OFF
AIN8 I Analog PE5 N/A
SSI1XDAT1 I/O LVCMOS PE5 (15) N/A
125 PD4 I/O LVCMOS – VDD OFF
AIN7 I Analog PD4 N/A
SSI1XDAT2 I/O LVCMOS PD4 (15) N/A
T3CCP0 I/O LVCMOS PD4 (3) N/A
U2Rx I LVCMOS PD4 (1) N/A
126 PD5 I/O LVCMOS – VDD OFF
AIN6 I Analog PD5 N/A
SSI1XDAT3 I/O LVCMOS PD5 (15) N/A
T3CCP1 I/O LVCMOS PD5 (3) N/A
U2Tx O LVCMOS PD5 (1) N/A
127 PD6 I/O LVCMOS – VDD OFF
AIN5 I Analog PD6 N/A
SSI2XDAT3 I/O LVCMOS PD6 (15) N/A
T4CCP0 I/O LVCMOS PD6 (3) N/A
U2RTS O LVCMOS PD6 (1) N/A
USB0EPEN O LVCMOS PD6 (5) N/A
128 PD7 I/O LVCMOS – VDD OFF
AIN4 I Analog PD7 N/A
NMI I LVCMOS PD7 (8) N/A
SSI2XDAT2 I/O LVCMOS PD7 (15) N/A
T4CCP1 I/O LVCMOS PD7 (3) N/A
U2CTS I LVCMOS PD7 (1) N/A
USB0PFLT I LVCMOS PD7 (5) N/A
(1) Signal Types: I = Input, O = Output, I/O = Input or Output.
(2) For details on buffer types, see Table 4-5.
(3) N/A = Not applicable
(4) State after reset release: PU = High impedance with an active pullup resistor, OFF = High impedance, N/A = not applicable