JAJSE27 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-41 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-42 100Base-TX Transmit Timing
          3. Table 5-43 10Base-T Normal Link Pulse Timing
          4. Table 5-44 Auto-Negotiation Fast Link Pulse (FLP) Timing
          5. Table 5-45 100Base-TX Signal Detect Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-46 ULPI Interface Timing
      16. 5.15.16 Analog Comparator
        1. Table 5-47 Analog Comparator Characteristics
        2. Table 5-48 Analog Comparator Characteristics
        3. Table 5-49 Analog Comparator Voltage Reference Characteristics
        4. Table 5-50 Analog Comparator Voltage Reference Characteristics
      17. 5.15.17 Pulse-Width Modulator (PWM)
        1. Table 5-51 PWM Timing Characteristics
      18. 5.15.18 Emulation and Debug
        1. Table 5-52 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

6.5.7.1 Direct Memory Access (DMA)

The DMA controller is known as micro-DMA (µDMA). The µDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The µDMA controller provides the following features:

  • Arm PrimeCell 32-channel configurable µDMA controller
  • Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes
    • Basic for simple transfer scenarios
    • Ping-pong for continuous data flow
    • Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from one request
  • Highly flexible and configurable channel operation
    • Independently configured and operated channels
    • Dedicated channels for supported on-chip modules
    • Flexible channel assignments
    • One channel each for receive and transmit path for bidirectional modules
    • Dedicated channel for software-initiated transfers
    • Per-channel configurable priority scheme
    • Optional software-initiated requests for any channel
  • Two levels of priority
  • Design optimizations for improved bus access performance between µDMA controller and the processor core
    • µDMA controller access is subordinate to core access
    • RAM striping
    • Peripheral bus segmentation
  • Data sizes of 8, 16, and 32 bits
  • Transfer size is programmable in binary steps from 1 to 1024
  • Source and destination address increment size of byte, halfword, word, or no increment
  • Maskable peripheral requests
  • Interrupt on transfer completion, with a separate interrupt per channel

Each DMA channel has up to nine possible assignments that are selected using the DMA Channel Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel.

Table 6-2 lists the µDMA channel mapping. The Encoding column lists the encoding for the respective DMACHMAPn bit field. Encodings 0x9 to 0xF are reserved. The Type column indicates if a particular peripheral uses a single request (S), burst request (B), or either (SB).

NOTE

Channels or encodings marked as Reserved cannot be used for µDMA transfers. Channels designated in the table as only "Software" are dedicated software channels. When only one software request is required in an application, dedicated software channels can be used. If multiple software requests in code are required, then peripheral channel software requests should be used for proper µDMA completion acknowledgement.

Table 6-2 µDMA Channel Assignments

ChannelEncoding
0 1 2 3 4 5678
Peripheral TypePeripheral TypePeripheral TypePeripheral TypePeripheral TypePeripheralTypePeripheralTypePeripheralTypePeripheralType
0 Reserved – UART2 RX SB Reserved – GPTimer 4A B Reserved – Reserved – I2C0 RX SB Reserved – Reserved –
1 Reserved – UART2 TX SB Reserved – GPTimer 4B B Reserved – Reserved – I2C0 TX SB Reserved – Reserved –
2 Reserved – GPTimer 3A B Reserved – Reserved – Reserved – Reserved – I2C1RX SB Reserved – Reserved –
3 Reserved – GPTimer 3B B Reserved – Software S Reserved – Reserved – I2C1 TX SB Reserved – Reserved –
4 Reserved – GPTimer 2A B Reserved – GPIO A B Reserved – SHA/MD5 0 Cin B I2C2 RX SB Reserved – Reserved –
5 Reserved – GPTimer 2B B Reserved – GPIO B B Reserved – SHA/MD5 0 Din B I2C2 TX SB Reserved – Reserved –
6 Reserved – GPTimer 2A B UART5 RX SB GPIO C B I2C0 RX SB SHA/MD5 0 Cout B Reserved – Reserved – Reserved –
7 Reserved – GPTimer 2B B UART5 TX SB GPIO D B I2C0 TX SB Reserved – Reserved – Reserved – Reserved –
8 UART0 RX SB UART1 RX SB Reserved – GPTimer 5A B I2C1RX SB Reserved – Reserved – Reserved – Reserved –
9 UART0 TX SB UART1 TX SB Reserved – GPTimer 5B B I2C1 TX SB Reserved – Reserved – Reserved – Reserved –
10 SSI0 RX SB SSI1 RX SB UART6 RX SB Reserved – I2C2 RX SB Reserved – Reserved – GPTimer 6A B Reserved –
11 SSI0 TX SB SSI1 TX SB UART6 TX SB Reserved – I2C2 TX SB Reserved – Reserved – GPTimer 6B B Reserved –
12 Reserved – UART2 RX SB SSI2 RX SB Reserved – GPIO K B AES0 Cin B Reserved – GPTimer 7A B Reserved –
13 Reserved – UART2 TX SB SSI2 TX SB Reserved – GPIO L B AES0 Cout B Reserved – GPTimer 7B B Reserved –
14 ADC0 SS0 SB GPTimer 2A B SSI3 RX SB GPIO E B GPIO M B AES0 Din B Reserved – Reserved – Reserved –
15 ADC0 SS1 SB GPTimer 2B B SSI3 TX SB GPIO F B GPIO N B AES0 Dout B Reserved – Reserved – Reserved –
16 ADC0 SS2 SB Reserved – UART3 RX SB Reserved – GPIO P B Reserved – Reserved – Reserved – Reserved –
17 ADC0 SS3 SB Reserved – UART3 TX SB Reserved – Reserved – Reserved – Reserved – Reserved – Reserved –
18 GPTimer 0A B GPTimer 1A B UART4 RX SB GPIO B B I2C3 RX SB Reserved – Reserved – Reserved – Reserved –
19 GPTimer 0B B GPTimer 1B B UART4 TX SB GPIO G B I2C3 TX SB Reserved – Reserved – Reserved – Reserved –
20 GPTimer 1A B EPI0 RX Software B UART7 RX SB GPIO H B I2C4 RX SB DES0 Cin B Reserved – Reserved – Reserved –
21 GPTimer 1B B EPI0 TX Software B UART7 TX SB GPIO J B I2C4 TX SB DES0 Din B Reserved – Reserved – Reserved –
22 UART1 RX SB Software B Reserved – Software B I2C5 RX SB DES0 Dout B Reserved – Reserved – I2C8 RX B
23 UART1 TX SB Software B Reserved – Software B I2C5 TX SB Reserved – Reserved – Reserved – I2C8 TX B
24 SSI1 RX SB ADC1 SS0 SB Reserved – Reserved – GPIO Q B Reserved – Reserved – Reserved – I2C9 RX B
25 SSI1 TX SB ADC1 SS1 SB Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – I2C9 TX B
26 Software B ADC1 SS2 SB Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – I2C6 RX B
27 Software B ADC1 SS3 SB Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – I2C6 TX B
28 Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – I2C7 RX B
29 Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – I2C7 TX B
30 Software B Software B Reserved – Software B Reserved – Reserved – Reserved – EPI0 RX B Reserved –
31 Reserved – Reserved – Reserved – Reserved B Reserved – Reserved – Reserved – EPI0 TX B Reserved –