JAJSE28B October   2017  – August 2018 UCC27710

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
    1.     標準的な伝播遅延の比較
  5. 5 改訂履歴
  6. 6 概要（続き）
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Dynamic Electrical Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD and Under Voltage Lockout
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Level Shift
      6. 9.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 9.3.7 Parasitic Diode Structure
    4. 9.4 Device Functional Modes
      1. 9.4.1 Minimum Input Pulse Operation
      2. 9.4.2 Output Interlock and Dead Time
      3. 9.4.3 Operation Under 100% Duty Cycle Condition
      4. 9.4.4 Operation Under Negative HS Voltage Condition
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 10.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 10.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 10.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 10.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 10.2.2.6 Selecting Bootstrap Diode
        7. 10.2.2.7 Estimate the UCC27710 Power Losses (PUCC27710)
        8. 10.2.2.8 Estimating Junction Temperature
        9. 10.2.2.9 Operation With IGBT's
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.4.4 Operation Under Negative HS Voltage Condition

A typical half-bridge configuration with UCC27710 is shown in Figure 40. There are parasitic inductances in the power circuit from die bonding and pinning in QT/QB and PCB tracks of power circuit, the parasitic inductances are labeled LK1,2,3,4.

During switching of HS caused by turning off HO, the current path of power circuit is changed to current path 2 from current path 1. This is known as current commutation. The current across LK3, LK4 and body diode of QB pulls HS lower than COM. The negative voltage of HS with respect to COM causes a logic error of HO if the driver cannot handle negative voltage of HS. However, the UCC27710 offers robust operation under these conditions of negative voltage on HS.

UCC27710 hsneg_slusdo5.gifFigure 40. HS Negative Voltage In Half-Bridge Configuration

The level shifter circuit is with respect to COM (refer to Functional Block Diagram), the voltage from HB to COM is the supply voltage of level shifter. Under the condition of HS is negative voltage with respect to COM, the voltage of HB-COM is decreased, as shown in Figure 41. There is a minimum operational supply voltage of level shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HI signal to HO. The minimum supply voltage of level shifter of UCC27710 is 4 V, so the recommended HS specification is dependent on HB-HS. The specification of recommended HS is –11 V at HB – HS = 15 V.

In general, HS can operate until -11 V when HB – HS = 15 V as the ESD structure in Figure 35 allows a maximum voltage difference of 20 V between both pins. If HB-HS voltage is different, the minimum HS voltage changes accordingly.

UCC27710 level_slusdo5.gifFigure 41. Level Shifter Supply Voltage with Negative HS

NOTE

Logic operational for HS of –11 V to 600 V at HB – HS = 15 V

The capability of a typical UCC27710 device to operate under a negative voltage condition in HS pin is reported in Figure 43. The test method is shown in Figure 42.

UCC27710 hsneg2_slusdo5.gifFigure 42. Negative Voltage Test Method
UCC27710 NTSOA.gifFigure 43. HS Negative Voltage Chart
Pulse Width vs HS Negative Voltage