9.1.6 Application for SYNC
The requirements for SYNC depend on certain setup conditions. In cases where the SYNC is not timing critical, the setup can be done through software by toggling the VCO_PHASE_SYNC_EN bit from 0 to 1. When the SYNC is timing critical, then setup must be done through the SYNC pin and the setup and hold times for the OSCin pin are critical.
The procedure for using SYNC in different SYNC categories is shown in Table 137.
Table 137. Procedure for Using SYNC
CATEGORY |
CHARACTERISTIC |
SETUP PROCEDURE |
1a |
- SYNC not required.
- SYNC mode not required.
|
- Setup as usual.
- Program all the registers as usual. The phase relationship between OSCin and fOUT will always be deterministic.
|
1b |
- SYNC not required.
- SYNC mode required.
|
- Set N = N' / 2, where N' is the normal N divider value.
- Program all the registers with R0 VCO_PHASE_SYNC_EN = 1.
|
2 |
- SYNC required.
- SYNC timing not critical.
- No limitation on fOSCin.
|
- Setup as usual.
- Program all the registers as usual. The device is now locked.
- Program N = N' / 2, where N' is the normal (original) N divider value.
- Program R0 with VCO_PHASE_SYNC_EN = 1.
- Program N = N'.
- Program R0 with VCO_PHASE_SYNC_EN = 0.
- Alternatively, step 3 to 6 can be replaced by applying a SYNC signal (0 → 1 transition) to the SYNC pin and the timing on this in not critical.
|
3 |
- SYNC required.
- SYNC timing critical.
- fOSCin ≤ 100 MHz
|
- Ensure that the maximum fOSCin for SYNC is not violated and there are hardware accommodations to use the SYNC pin.
- If neither OUTA_MUX nor OUTB_MUX is equal to 0 (Channel divider output), program N divider as usual.
- If one of the OUTA_MUX or OUTB_MUX is equal to 1, set N = N' / 2, where N' is the normal N divider (integer + fraction) value.
- Program all the registers with R0 VCO_PHASE_SYNC_EN = 1.
- Apply a SYNC signal (0 → 1 transition) to the SYNC pin. The timing of the SYNC signal as shown in Timing Requirements must be obey.
|
Set these bits to drive the SYNC pin with a LVDS signal:
- Set INPIN_FMT to 1 or 3 to enable LVDS input
- Set INPIN_LVL to one of the options
- Set INPIN_HYST, if necessary
The LVDS driver that is driving the SYNC pin should be configured as shown in Figure 171: