JAJSE32B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
SYSREF consists of multiple dividers and a delay circuitry. The dividers include two fixed value dividers, a Pre-SR divider (SYSREF_DIV_PRE), and a Post-SR divider (SYSREF_DIV).
SYSREF output frequency, fSYSREF, is calculated by Equation 7:
The delay circuitry is consist of 4 counters (JESD_DAC1_CTRL, JESD_DAC2_CTRL, JESD_DAC3_CTRL, and JESD_DAC4_CTRL). Altogether, there are 200 useful programmable steps and each step is approximately a 5 ps (Pre-SR divider = 2) or 10 ps (Pre-SR divider = 4) delay. The values of the counters must be set in accordance to Table 140.
DELAY STEP NUMBER | JESD_DAC1_CTRL | JESD_DAC2_CTRL | JESD_DAC3_CTRL | JESD_DAC4_CTRL |
---|---|---|---|---|
0 | 36 | 27 | 0 | 0 |
… | ||||
36 | 0 | 63 | 0 | 0 |
37 | 0 | 62 | 1 | 0 |
… | ||||
99 | 0 | 0 | 63 | 0 |
100 | 0 | 0 | 62 | 1 |
… | ||||
162 | 0 | 0 | 0 | 63 |
163 | 1 | 0 | 0 | 62 |
… | ||||
200 | 38 | 0 | 0 | 25 |
> 200 | Invalid | Invalid | Invalid | Invalid |
Table 141 summarizes the usage boundaries of all functional blocks in SYSREF.
PARAMETER | VALUE | NOTES |
---|---|---|
Pre-SR divider | 1 (Bypassed), 2, 4 | |
Post-SR divider | 4, 6, 8, 10, …, 4096, 4098 | Input frequency range: 400 to 2300 MHz |
Number of SYSREF pulse in Pulsed mode | 1, 2, 3, …, 14, 15 | |
Number of delay step | 0 (No additional delay), 1, 2, 3, …, 199, 200 |
Since SYSREF operation requires enabling the VCO_PHASE_SYNC_EN bit, during programming, set N = N' / 2, where N' is the normal N divider value.