JAJSE32B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
The MUXout pin can be configured to output a signal that gives an indication for the PLL being locked. If the MUXout pin is configured as a lock detect output (MUXOUT_LD_SEL = 1), the MUXout pin output is a logic HIGH voltage when the device is locked. When the device is unlocked, the MUXout pin output is a logic LOW voltage.
There are options to select the definition of PLL being locked. If LD_TYPE = 0, lock detect asserts a HIGH output after the VCO has finished calibration and the LD_DLY timeout counter is finished. If LD_TYPE = 1, in addition to the VCO calibration and counter check, lock detect will assert a HIGH output if the VCO tuning voltage is also within an acceptable limits.