8.6 Register Maps
REG. |
DATA[15:0] |
POR |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
R0 |
RAMP_EN |
VCO_PHASE_SYNC_EN |
1 |
0 |
ADD_HOLD |
0 |
OUT_MUTE |
FCAL_HPFD_ADJ |
FCAL_LPFD_ADJ |
1 |
FCAL_EN |
MUXOUT_
LD_SEL |
RESET |
POWER
DOWN |
00221Ch |
R1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
CAL_CLK_DIV |
010808h |
R2 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
020500h |
R3 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
030782h |
R4 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
040A43h |
R5 |
0 |
0 |
1 |
IPBUF_
TYPE |
IPBUF_
TERM |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0530C8h |
R6 |
LDO_DLY |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
06C802h |
R7 |
0 |
OUT_
FORCE |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0700B2h |
R8 |
0 |
VCO_
DACISET_
FORCE |
1 |
0 |
VCO_
CAPCTRL_
FORCE |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
082000h |
R9 |
0 |
MULT_HI |
0 |
OSC_2X |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
090004h |
R10 |
0 |
0 |
0 |
1 |
MULT |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0A10F8h |
R11 |
1 |
0 |
1 |
1 |
PLL_R |
1 |
0 |
0 |
0 |
0BB018h |
R12 |
0 |
1 |
0 |
1 |
PLL_R_PRE |
0C5001h |
R13 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0D4000h |
R14 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
CPG |
0 |
0 |
0 |
0E1840h |
R15 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0F060Eh |
R16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
VCO_DACISET |
100080h |
R17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
VCO_DACISET_STRT |
110096h |
R18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
120064h |
R19 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
VCO_CAPCTRL |
1327B7h |
R20 |
0 |
1 |
VCO_SEL |
VCO_SEL_
FORCE |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
143048h |
R21 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
150409h |
R22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
160001h |
R23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
17007Ch |
R24 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
18071Ah |
R25 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
190624h |
R26 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1A0808h |
R27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1B0002h |
R28 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1C0488h |
R29 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1D18C6h |
R30 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1E18C6h |
R31 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1FC3E6h |
R32 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
2005BFh |
R33 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
211E01h |
R34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
PLL_N[18:16] |
220010h |
R35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
230004h |
R36 |
PLL_N |
240028h |
R37 |
MASH_
SEED_EN |
0 |
PFD_DLY_SEL |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
250205h |
R38 |
PLL_DEN[31:16] |
26FFFFh |
R39 |
PLL_DEN[15:0] |
27FFFFh |
R40 |
MASH_SEED[31:16] |
280000h |
R41 |
MASH_SEED[15:0] |
290000h |
R42 |
PLL_NUM[31:16] |
2A0000h |
R43 |
PLL_NUM[15:0] |
2B0000h |
R44 |
0 |
0 |
OUTA_PWR |
OUTB_
PD |
OUTA_
PD |
MASH_
RESET_N |
0 |
0 |
MASH_ORDER |
2C22A2h |
R45 |
1 |
1 |
0 |
OUTA_MUX |
1 |
1 |
0 |
0 |
0 |
OUTB_PWR |
2DC622h |
R46 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
OUTB_MUX |
2E07F0h |
R47 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
2F0300h |
R48 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
3003E0h |
R49 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
314180h |
R50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
320080h |
R51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
330080h |
R52 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
340420h |
R53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
350000h |
R54 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
360000h |
R55 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
370000h |
R56 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
380000h |
R57 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
390000h |
R58 |
INPIN_
IGNORE |
INPIN_
HYST |
INPIN_LVL |
INPIN_FMT |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
3A8001h |
R59 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
LD_TYPE |
3B0001h |
R60 |
LD_DLY |
3C03E8h |
R61 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
3D00A8h |
R62 |
DBLBUF_
EN_5 |
DBLBUF_
EN_4 |
DBLBUF_
EN_3 |
DBLBUF_
EN_2 |
DBLBUF_
EN_1 |
DBLBUF_
EN_0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
3E00AFh |
R63 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
3F0000h |
R64 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
401388h |
R65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
410000h |
R66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
4201F4h |
R67 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
430000h |
R68 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
4403E8h |
R69 |
MASH_RST_COUNT[31:16] |
450000h |
R70 |
MASH_RST_COUNT[15:0] |
46C350h |
R71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SYSREF_DIV_PRE |
SYSREF_
PULSE |
SYSREF_EN |
SYSREF_
REPEAT |
0 |
1 |
470080h |
R72 |
0 |
0 |
0 |
0 |
0 |
SYSREF_DIV |
480001h |
R73 |
0 |
0 |
0 |
0 |
JESD_DAC2_CTRL |
JESD_DAC1_CTRL |
49003Fh |
R74 |
SYSREF_PULSE_CNT |
JESD_DAC4_CTRL |
JESD_DAC3_CTRL |
4A0000h |
R75 |
0 |
0 |
0 |
0 |
1 |
CHDIV |
0 |
0 |
0 |
0 |
0 |
0 |
4B0800h |
R76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
4C000Ch |
R77 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
4D0000h |
R78 |
0 |
0 |
0 |
0 |
RAMP_
THRESH[32] |
0 |
QUICK_
RECAL_EN |
VCO_CAPCTRL_STRT |
1 |
4E0064h |
R79 |
RAMP_THRESH[31:16] |
4F0000h |
R80 |
RAMP_THRESH[15:0] |
500000h |
R81 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
RAMP_LIMIT_HIGH[32] |
510000h |
R82 |
RAMP_LIMIT_HIGH[31:16] |
520000h |
R83 |
RAMP_LIMIT_HIGH[15:0] |
530000h |
R84 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
RAMP_LIMIT_LOW[32] |
540000h |
R85 |
RAMP_LIMIT_LOW[31:16] |
550000h |
R86 |
RAMP_LIMIT_LOW[15:0] |
560000h |
R87 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
570000h |
R88 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
580000h |
R89 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
590000h |
R90 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5A0000h |
R91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5B0000h |
R92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5C0000h |
R93 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5D0000h |
R94 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5E0000h |
R95 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
5F0000h |
R96 |
RAMP_
BURST_EN |
RAMP_BURST_COUNT |
0 |
0 |
600000h |
R97 |
RAMP0_RST |
0 |
0 |
0 |
0 |
RAMP_TRIGB |
RAMP_TRIGA |
0 |
RAMP_BURST_TRIG |
610000h |
R98 |
RAMP0_INC[29:16] |
0 |
RAMP0_DLY |
620000h |
R99 |
RAMP0_INC[15:0] |
630000h |
R100 |
RAMP0_LEN |
640000h |
R101 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
RAMP1_
DLY |
RAMP1_
RST |
RAMP0_
NEXT |
0 |
0 |
RAMP0_NEXT_TRIG |
650000h |
R102 |
0 |
0 |
RAMP1_INC[29:16] |
660000h |
R103 |
RAMP1_INC[15:0] |
670000h |
R104 |
RAMP1_LEN |
680000h |
R105 |
RAMP_DLY_CNT |
RAMP_
MANUAL |
RAMP1_
NEXT |
0 |
0 |
RAMP1_NEXT_TRIG |
694440h |
R106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
RAMP_
TRIG_CAL |
0 |
RAMP_SCALE_COUNT |
6A0007h |
R107 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
6B0000h |
R108 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
6C0000h |
R109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
6D0000h |
R110 |
0 |
0 |
0 |
0 |
0 |
rb_LD_VTUNE |
0 |
rb_VCO_SEL |
0 |
0 |
0 |
0 |
0 |
6E0000h |
R111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
rb_VCO_CAPCTRL |
6F0000h |
R112 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
rb_VCO_DACISET |
700000h |
R113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
710000h |
R114 |
0 |
1 |
1 |
1 |
1 |
FSK_EN |
0 |
0 |
0 |
FSK_SPI_LEVEL |
FSK_SPI_DEV_SEL |
FSK_MODE_SEL |
727800h |
R115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
FSK_DEV_SCALE |
0 |
0 |
0 |
730000h |
R116 |
FSK_DEV0 |
740000h |
R117 |
FSK_DEV1 |
750000h |
R118 |
FSK_DEV2 |
760000h |
R119 |
FSK_DEV3 |
770000h |
R120 |
FSK_DEV4 |
780000h |
R121 |
FSK_DEV5 |
790000h |
R122 |
FSK_DEV6 |
7A0000h |
R123 |
FSK_DEV7 |
7B0000h |
R124 |
FSK_SPI_FAST_DEV |
7C0000h |
R125 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
7D2288h |
Table 7 lists the access codes for the LMX2572 registers.
Table 7. Access Type Codes
ACCESS TYPE |
CODE |
DESCRIPTION |
Read Type |
R |
R |
Read |
Write Type |
W |
W |
Write |
Reset or Default Value |
-n |
|
Value after reset |