JAJSE32B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAMP_EN | VCO_PHASE_SYNC_EN | 1 | 0 | ADD_HOLD | 0 | OUT_MUTE | FCAL_HPFD_ADJ | FCAL_LPFD_ADJ | 1 | FCAL_EN | MUXOUT_LD_SEL | RESET | POWERDOWN | ||
| R/W-0h | R/W-0h | R/W-2h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RAMP_EN | R/W | 0h | Enables frequency ramping. The action of programming register R0 with RAMP_EN = 1 starts the ramping. Be aware that this is in the same register as FCAL_EN, so toggling this bit also can active the ramping if RAMP_EN = 1. RAMP_EN applies to both automatic and manual ramping modes.
0: Normal operation 1: Starts frequency ramping |
| 14 | VCO_PHASE_SYNC_EN | R/W | 0h | Enables phase sync mode. In this state, part of the channel divider is put in the feedback path to ensure deterministic phase. The action of toggling this bit from 0 to 1 also sends an asynchronous SYNC pulse.
0: Normal operation 1: Phase sync mode |
| 13 - 12 | R/W | 2h | Program 2h to this field. | |
| 11 | ADD_HOLD | R/W | 0h | Freeze the register address in Block Programming. See Block Programming for details. |
| 10 | R/W | 0h | Program 0h to this field. | |
| 9 | OUT_MUTE | R/W | 1h | Mutes RF outputs (RFoutA and RFoutB) when the VCO is calibrating.
0: Disabled 1: Muted |
| 8 - 7 | FCAL_HPFD_ADJ | R/W | 0h | Set this field in accordance to the phase detector frequency for optimal VCO calibration.
0: fPD ≤ 37.5 MHz 1: 37.5 MHz < fPD ≤ 75 MHz 2: 75 MHz < fPD ≤ 100 MHz 3: fPD > 100 MHz |
| 6 - 5 | FCAL_LPFD_ADJ | R/W | 0h | Set this field in accordance to the phase detector frequency for optimal VCO calibration.
0: fPD ≥ 10 MHz 1: 10 MHz > fPD ≥ 5 MHz 2: 5 MHz > fPD ≥ 2.5 MHz 3: fPD < 2.5 MHz |
| 4 | R/W | 1h | Program 1h to this field. | |
| 3 | FCAL_EN | R/W | 1h | Enables and activates VCO frequency calibration. Writing register R0 with this bit set to a 1 enables and triggers the VCO frequency calibration. Writing 0 to this field is prohibited.
0: Invalid 1: Enabled |
| 2 | MUXOUT_LD_SEL | R/W | 1h | Selects the functionality of the MUXout pin.
0: Register readback 1: Lock detect |
| 1 | RESET | R/W | 0h | Resets all registers to silicon default values. This bit is self-clearing.
0: Normal operation 1: Reset |
| 0 | POWERDOWN | R/W | 0h | Powers down the device.
0: Normal operation 1: Power down |