JAJSE32B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CE | 1 | Input | Chip enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the device. |
CPout | 12 | Output | Charge pump output. Place C1 of loop filter close to this pin. |
CSB | 24 | Input | SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic. |
DAP | — | Ground | RF ground. |
GND | 2, 4, 25, 31, 34, 39 | Ground | VCO ground. |
6, 14, 40 | Ground | Digital ground. | |
13 | Ground | Charge pump ground. | |
MUXout | 20 | Output | Multiplexed output pin. Configurable between lock detect and register readback. |
OSCinM | 9 | Input | Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling. |
OSCinP | 8 | Input | Reference input clock (+). High impedance self-biasing pin. Requires AC-coupling. |
RampClk | 30 | Input | Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode. High impedance CMOS input. 1.8-V to 3.3-V logic. |
RampDir | 32 | Input | Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping mode. High impedance CMOS input. 1.8-V to 3.3-V logic. |
RFoutAM | 22 | Output | Differential output A (–). Low impedance output. Requires AC-coupling. |
RFoutAP | 23 | Output | Differential output A (+). Low impedance output. Requires AC-coupling. |
RFoutBM | 18 | Output | Differential output B (–). Low impedance output. Requires AC-coupling. Configurable between RF output or SYSREF output. |
RFoutBP | 19 | Output | Differential output B (+). Low impedance output. Requires AC-coupling. Configurable between RF output or SYSREF output. |
SCK | 16 | Input | SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic. |
SDI | 17 | Input | SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic. |
SYNC | 5 | Input | Phase synchronization trigger. Configurable to accept CMOS input (1.8-V to 3.3-V logic) or differential input. |
SysRefReq | 28 | Input | SYSREF request for JESD204B support. Configurable to accept CMOS input (1.8-V to 3.3-V logic) or differential input. |
VbiasVARAC | 33 | Bypass | VCO Varactor bias. Connect a 10-µF decoupling capacitor to VCO ground. |
VbiasVCO | 3 | Bypass | VCO bias. Connect a 470-nF (X7R) decoupling capacitor to VCO ground as close to this pin as possible. |
VbiasVCO2 | 27 | Bypass | VCO bias. Connect a 100-nF (X7R) decoupling capacitor to VCO ground. |
VccBUF | 21 | Supply | Supply for output buffers. Connect a 0.1-µF decoupling capacitor to RF ground. |
VccCP | 11 | Supply | Supply for charge pump. Connect a 0.1-µF decoupling capacitor to charge pump ground. |
VccDIG | 7 | Supply | Digital power supply. Connect a 0.1-µF decoupling capacitor to digital ground. |
VccMASH | 15 | Supply | Digital power supply. Connect a 1-µF decoupling capacitor to digital ground. |
VccVCO | 37 | Supply | Supply for VCO. Connect a 1-µF decoupling capacitor to VCO ground. |
VccVCO2 | 26 | Supply | Supply for VCO. Connect a 1-µF decoupling capacitor to VCO ground. |
VrefVCO | 36 | Bypass | VCO supply reference. Connect a 10-µF decoupling capacitor to VCO ground. |
VrefVCO2 | 29 | Bypass | VCO supply reference. Connect a 10-µF decoupling capacitor to VCO ground. |
VregIN | 10 | Bypass | Input reference path regulator output. Connect a 1-µF decoupling capacitor to RF ground as close to this pin as possible. |
VregVCO | 38 | Bypass | VCO regulator node. Connect a 10-nF decoupling capacitor to VCO ground. |
Vtune | 35 | Input | VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground. See External Loop Filter for details. |