JAJSE43E March   2017  – May 2021 CC3120MOD

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3120MOD Pin Diagram
    2. 7.2 Pin Attributes
      1.      11
    3. 7.3 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption Summary
    5. 8.5  TX Power and IBAT versus TX Power Level Settings
    6. 8.6  Brownout and Blackout Conditions
    7. 8.7  Electrical Characteristics
    8. 8.8  WLAN Receiver Characteristics
    9. 8.9  WLAN Transmitter Characteristics
    10. 8.10 Reset Requirement
    11. 8.11 Thermal Resistance Characteristics for MOB Package
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1 Power-Up Sequencing
      2. 8.12.2 Power-Down Sequencing
      3. 8.12.3 Device Reset
      4. 8.12.4 Wakeup From HIBERNATE Mode Timing
    13. 8.13 External Interfaces
      1. 8.13.1 SPI Host Interface
      2. 8.13.2 Host UART Interface
        1. 8.13.2.1 5-Wire UART Topology
        2. 8.13.2.2 4-Wire UART Topology
        3. 8.13.2.3 3-Wire UART Topology
      3. 8.13.3 External Flash Interface
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Module Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
        1. 9.2.2.1 Security
      3. 9.2.3 Host Interface and Driver
      4. 9.2.4 System
    3. 9.3 Power-Management Subsystem
      1. 9.3.1 VBAT Wide-Voltage Connection
    4. 9.4 Low-Power Operating Modes
      1. 9.4.1 Low-Power Deep Sleep
      2. 9.4.2 Hibernate
      3. 9.4.3 Shutdown
    5. 9.5 Restoring Factory Default Configuration
    6. 9.6 Device Certification and Qualification
      1. 9.6.1 FCC Certification and Statement
      2. 9.6.2 Industry Canada (IC) Certification and Statement
      3. 9.6.3 ETSI/CE Certification
      4. 9.6.4 Japan MIC Certification
      5. 9.6.5 SRRC Certification and Statement
    7. 9.7 Module Markings
    8. 9.8 End Product Labeling
    9. 9.9 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
      2. 10.1.2 Power Supply Decoupling and Bulk Capacitors
      3. 10.1.3 Reset
      4. 10.1.4 Unused Pins
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General Layout Recommendations
      2. 10.2.2 RF Layout Recommendations
      3. 10.2.3 Antenna Placement and Routing
      4. 10.2.4 Transmission Line Considerations
  11. 11Environmental Requirements and Specifications
    1. 11.1 Temperature
      1. 11.1.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Development Tools and Software
    3. 12.3 Firmware Updates
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
    3. 13.3 Tape and Reel Information
      1. 13.3.1 Tape and Reel Specification

Table 7-1 Module Pin Attributes
PIN(1) DEFAULT FUNCTION STATE AT RESET AND HIBERNATE I/O
TYPE(2)		 DESCRIPTION
1 GND N/A – Ground
2 GND N/A – Ground
4 nHIB Hi-Z I Hibernate signal, active low. Ensure that the nHIB line does not float at any time.
5 HOST_SPI_CLK Hi-Z I Host interface SPI clock
6 HOST_SPI_DIN Hi-Z I Host interface SPI data input
7 HOST_SPI_DOUT Hi-Z O Host interface SPI data output
8 HOST_SPI_nCS Hi-Z I Host interface SPI chip select (active low)
11 HOST_INTR Hi-Z O Interrupt output
13 FLASH_SPI_MISO Hi-Z I External serial Flash interface: SPI data in
14 FLASH_SPI_nCS_IN Hi-Z O External serial Flash interface: SPI chip select (active low)
15 FLASH_SPI_CLK Hi-Z O External serial Flash interface: SPI clock
16 GND N/A – Ground
17 FLASH_SPI_MOSI Hi-Z O External serial Flash interface: SPI data out
23 SOP2 Hi-Z – SOP[2:0] used for factory restore. See Section 9.5.
24 SOP1 Hi-Z – SOP[2:0] used for factory restore. See Section 9.5.
27 GND N/A – Ground
28 GND N/A – Ground
30 GND N/A – Ground. Reference for RF signal
31 RF_BG Hi-Z I/O 2.4-GHz RF input/output
32 GND N/A – Ground. Reference for RF signal
34 SOP0 Hi-Z – SOP[2:0] used for factory restore. See Section 9.5.
35 nRESET Hi-Z I There is an internal 100 kΩ pull-up resistor option from the nRESET pin to VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the module. The following connection schemes are recommended:
  • Connect nRESET to a GPIO from the host only if nRESET will be in a defined state under all operating conditions. Leave VBAT_RESET unconnected to save power.
  • If nRESET cannot be in a defined state under all operating conditions, connect VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the internal pull-up resistor, a leakage current of 3.3 V / 100 kΩ is expected.
36 VBAT_RESET Hi-Z –
37 VBAT1 Hi-Z – Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
38 GND N/A – Ground
40 VBAT2 Hi-Z – Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
43 GND N/A – Ground
44 UART1_nRTS Hi-Z O UART interface to host (request to send)
46 UART1_TX Hi-Z O UART interface to host (transmit)
47 UART1_RX Hi-Z I UART interface to host (receive)
50 TEST_60 Hi-Z O Connect to external test point.
51 UART1_nCTS Hi-Z I UART interface to host (clear to send)
52 TEST_62 Hi-Z O Connect to external test point.
55 GND N/A – Thermal Ground
56 GND N/A – Thermal Ground
57 GND N/A – Thermal Ground
58 GND N/A – Thermal Ground
59 GND N/A – Thermal Ground
60 GND N/A – Thermal Ground
61 GND N/A – Thermal Ground
62 GND N/A – Thermal Ground
63 GND N/A – Thermal Ground
(1) Using a configuration file stored on Flash, the vendor can optionally block any possibility of bringing up AP using the FORCE_AP pin.
(2) I = Input, O = Output, RF = Radio frequency, I/O = Bidirectional