JAJSE43 データシート

JAJSE43E March 2017 – May 2021 CC3120MOD

PRODUCTION DATA

8.13.1 SPI Host Interface

The device interfaces to an external host using the SPI. The CC3120MOD module can interrupt the host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a speed of 20 MHz.

Figure 8-8 shows the SPI host interface.

Figure 8-8 SPI Host Interface

Table 8-4 lists the SPI host interface pins.

Table 8-4 SPI Host Interface

PIN NAME	DESCRIPTION
HOST_SPI_CLK	Clock (up to 20 MHz) from MCU host to CC3120MOD module
HOST_SPI_nCS	CS (active low) signal from MCU host to CC3120MOD module
HOST_SPI_MOSI	Data from MCU host to CC3120MOD module
HOST_INTR	Interrupt from CC3120MOD module to MCU host
HOST_SPI_MISO	Data from CC3120MOD module to MCU host
nHIB	Active-low signal that commands the CC3120MOD module to enter hibernate mode (lowest power state)

Figure 8-9 shows the host SPI timing diagram.

Figure 8-9 Host SPI Timing

Table 8-5 lists the host SPI timing parameters.

Table 8-5 Host SPI Timing Parameters

PARAMETER NUMBER	DESCRIPTION		MIN	MAX	UNIT
T1	F⁽¹⁾	Clock frequency at V_BAT = 3.3 V		20	MHz
T1	F⁽¹⁾	Clock frequency at V_BAT = 2.3 V		12	MHz
T2	t_clk⁽¹⁾⁽²⁾	Clock period	50		ns
T3	t_LP⁽¹⁾	Clock low period		25	ns
T4	t_HT⁽¹⁾	Clock high period		25	ns
T5	D⁽¹⁾	Duty cycle	45%	55%
T6	t_IS⁽¹⁾	RX data setup time	4		ns
T7	t_IH⁽¹⁾	RX data hold time	4		ns
T8	t_OD⁽¹⁾	TX data output delay		20	ns
T9	t_OH⁽¹⁾	TX data hold time		24	ns

(1) The timing parameter has a maximum load of 20 pf at 3.3 V.

(2) Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. The nCS signal can be deasserted 10 ns after the clock edge.