JAJSE88F November   2017  – February 2024 UCC21220 , UCC21220A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Thermal Derating Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21220 and UCC21220A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimating Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.12 Typical Characteristics

VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted.

GUID-58AF1981-F509-4A8C-81A3-4686986E8E90-low.gif
No LoadINA = INB = GND
Figure 6-3 VCCI Quiescent Current
GUID-62D6249E-176B-49E9-8C15-F6784BAF9DED-low.gif
Figure 6-5 VCCI Operating Current vs. Frequency
GUID-F1E11653-DD78-4294-B9B3-FCA86E83B9BC-low.gif
No Load
Figure 6-7 VDD Per Channel Operating Current - IVDDA/B)
GUID-43721FA3-C5CF-4C9E-91F4-346E45CF39DB-low.gif
Figure 6-9 VCCI UVLO Threshold Voltage
GUID-814331E9-2990-4BA9-BBDA-CAF7913BD3AE-low.gif
Figure 6-11 8-V VDD UVLO Threshold Voltage
GUID-51C6757E-7BDC-4381-B6F8-631B82170635-low.gif
Figure 6-13 5-V VDD UVLO Threshold Voltage
GUID-D4DBD2A1-4DD2-46F6-9360-4C48A2149C37-low.gif
Figure 6-15 INA/INB/DIS High and Low Threshold Voltage
GUID-C064E26C-0D18-45B4-8B09-0CF4F6C752B4-low.gif
Figure 6-17 OUT Pullup and Pulldown Resistance
GUID-73FBA543-ADFC-4B84-B689-6FBE65ED1379-low.gif
Figure 6-19 Propagation Delay Matching, Rising Edge, and Falling Edge
GUID-464FFECC-59B1-4BB0-9943-3B5828699592-low.gif
CL = 1.8 nF
Figure 6-21 Rise Time and Fall Time
GUID-BCD3BF94-64E2-4D89-8B41-4354724D7808-low.gif
Figure 6-23 OUTPUT Active Pulldown Voltage
GUID-6FBDC40D-AE8A-444D-AD70-86E2988C7D0B-low.gif
Figure 6-4 VCCI Operating Current - IVCCI
GUID-674848C6-F153-4914-BE08-F003378ED5B8-low.gif
No LoadINA = INB = GND
Figure 6-6 VDD Per Channel Quiescent Current (IVDDA, IVDDB)
GUID-2AAA89C5-719C-4053-8B63-80BDE75C68EA-low.gif
No LoadINA and INB both switching
Figure 6-8 Per Channel Operating Current (IVDDA/B) vs. Frequency
GUID-B52ABF48-65AE-4707-82F2-F5C4E919212D-low.gif
Figure 6-10 VCCI UVLO Threshold Hysteresis Voltage
GUID-61C38D46-F166-45E8-9AE3-B127B14FD994-low.gif
Figure 6-12 8-V VDD UVLO Threshold Hysteresis
GUID-D2671FCB-C9EF-40FC-B61E-82F4DAD16E56-low.gif
A.
Figure 6-14 5-V VDD UVLO Threshold Hysteresis
GUID-DCEAAB12-9D0F-4485-814D-516477BCB11C-low.gif
Figure 6-16 INA/INB/DIS High and Low Threshold Hysteresis
GUID-B1E8569A-7095-4CA3-98A8-F180265B7B4D-low.gif
Figure 6-18 Propagation Delay, Rising Edge, and Falling Edge
GUID-44EB1797-82CA-4B8E-A97C-DD7238A0C9AD-low.gif
tPDLH – tPDHL
Figure 6-20 Pulse Width Distortion
GUID-335CA38D-45D6-4B2C-B9BC-F84A0101E936-low.gif
Figure 6-22 DISABLE Response Time
GUID-6C106D8F-4DE2-47B2-9530-F59A57982564-low.gif
Figure 6-24 Minimum Pulse that Changes Output