JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

At VDD = 12 VDC, CVG = 0 pF, CREG = 2.2 µF, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to VS, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS SUPPLY
IVDDSTART VDD current, REG undervoltage VDD = 4 V, VD = 0 V 50 105 150 μA
IVDDRUN VDD current, run VDD = 12 V 0.5 0.92 1.5 mA
VDD = 5 V 0.5 0.9 1.5 mA
IVDDSTBY VDD current, standby mode VDD = 12 V, VD = 1 V 200 390 650 μA
VDD = 5 V, VD = 1 V 200 320 500 μA
UNDERVOLTAGE LOCKOUT (UVLO)
VREGON REG turn-on threshold Turn-on detected by IVDD rising 4.15 4.5 4.87 V
VREGOFF REG turn-off threshold Turn-off detected by IVDD falling 3.65 4 4.25 V
VREGHYST UVLO hysteresis VREGHYST = VREGON – VREGOFF 0.425 0.5 0.575 V
MOSFET VOLTAGE SENSING
VTHVGON VG turn-on threshold VD falling, TJ = 25°C –300 –240 –175 mV
VTHVGOFF VG turn-off threshold VD rising, TJ = 25°C –20 -9 –2 mV
VD rising, –40°C ≤TJ ≤ 125°C –30 –9 –2
VTHARM VG re-arming threshold VD rising 0.4 0.5 0.6 V
IVDBIAS_ON VD pin bias current when VG is high (SR is on) VVD = –50 mV, VVG = VGH –1 0 1 µA
IVDBIAS_OFF VD pin bias current when VG is low (SR is off) VVD = –150 mV, VVG = VGL, TJ = 25°C –6 –2 µA
VVD = –150 mV, VVG = VGL, –40°C ≤TJ ≤ 125°C –10
IVDLK VD pin leakage current VVD = 200 V 0.06 2 µA
GATE DRIVER
RSOURCE VG pull-up resistance IVG = –20 mA 5.7 10 Ω
RSINK VG pull-down resistance IVG = 100 mA 0.45 1 Ω
VGH VG clamp level 8.55 9.4 10.26 V
VGL VG output low voltage IVG = 100 mA, VDD = 12 V 60 150 mV
VOLGUV VG output low voltage in UVLO IVG = 25 mA, VDD = 4 V 0.7 V
IVGPU Gate driver maximum source current 1(1) A
IVGPD Gate driver maximum sink current (1) 4 A
REG SUPPLY
VREG REG pin regulation level ILOAD_REG = 0 mA 8.55 9.4 10.26 V
VREGLG Load regulation on REG ILOAD_REG= 10 mA to 0 mA 0.016 0.1 V
VREGDO REG drop-out on pass-through mode VDD = 5 V, ILOAD_REG= 10 mA 0.28 0.45 V
IREGSC REG short-circuit current VREG = 0 V 1 5.2 15 mA
IREGLIM REG current limit VREG = 8 V 25 42 62 mA
(1) Specified by design