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  • LMK05028 EEPROM 搭載の低ジッタ デュアルチャネル ネットワーク同期クロック

    • JAJSER5B February   2018  – February 2025 LMK05028

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  • LMK05028 EEPROM 搭載の低ジッタ デュアルチャネル ネットワーク同期クロック
  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1. 4.1 Device Start-Up Modes
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 7.2 Functional Block Diagrams
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 3-Loop Mode
        1. 7.2.2.1 PLL Output Clock Phase Noise Analysis in 3-Loop Mode
      3. 7.2.3 2-Loop REF-DPLL Mode
      4. 7.2.4 2-Loop TCXO-DPLL Mode
      5. 7.2.5 PLL Configurations for Common Applications
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO_P/N)
      2. 7.3.2  TCXO/OCXO Input (TCXO_IN)
      3. 7.3.3  Reference Inputs (INx_P/N)
      4. 7.3.4  Clock Input Interfacing and Termination
      5. 7.3.5  Reference Input Mux Selection
        1. 7.3.5.1 Automatic Input Selection
        2. 7.3.5.2 Manual Input Selection
      6. 7.3.6  Hitless Switching
      7. 7.3.7  Gapped Clock Support on Reference Inputs
      8. 7.3.8  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.8.1 XO Input Monitoring
        2. 7.3.8.2 TCXO Input Monitoring
        3. 7.3.8.3 Reference Input Monitoring
          1. 7.3.8.3.1 Reference Validation Timer
          2. 7.3.8.3.2 Amplitude Monitor
          3. 7.3.8.3.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.8.3.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.8.3.5 Frequency Monitoring
        4. 7.3.8.4 PLL Lock Detectors
        5. 7.3.8.5 Tuning Word History
        6. 7.3.8.6 Status Outputs
        7. 7.3.8.7 Interrupt
      9. 7.3.9  PLL Channels
        1. 7.3.9.1  PLL Frequency Relationships
        2. 7.3.9.2  Analog PLL (APLL)
        3. 7.3.9.3  APLL XO Doubler
        4. 7.3.9.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.9.5  APLL Loop Filter
        6. 7.3.9.6  APLL Voltage Controlled Oscillator (VCO)
          1. 7.3.9.6.1 VCO Calibration
        7. 7.3.9.7  APLL VCO Post-Dividers (P1, P2)
        8. 7.3.9.8  APLL Fractional N Divider (N) With SDM
        9. 7.3.9.9  REF-DPLL Reference Divider (R)
        10. 7.3.9.10 TCXO/OCXO Input Doubler and M Divider
        11. 7.3.9.11 TCXO Mux
        12. 7.3.9.12 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
        13. 7.3.9.13 REF-DPLL and TCXO-DPLL Loop Filter
        14. 7.3.9.14 REF-DPLL and TCXO-DPLL Feedback Dividers
      10. 7.3.10 Output Clock Distribution
      11. 7.3.11 Output Channel Muxes
        1. 7.3.11.1 TCXO/Ref Bypass Mux
      12. 7.3.12 Output Dividers
      13. 7.3.13 Clock Outputs (OUTx_P/N)
        1. 7.3.13.1 AC-Differential Output (AC-DIFF)
        2. 7.3.13.2 HCSL Output
        3. 7.3.13.3 LVCMOS Output (1.8 V, 2.5 V)
        4. 7.3.13.4 Output Auto-Mute During LOL or LOS
      14. 7.3.14 Glitchless Output Clock Start-Up
      15. 7.3.15 Clock Output Interfacing and Termination
      16. 7.3.16 Output Synchronization (SYNC)
      17. 7.3.17 Zero-Delay Mode (ZDM) Configuration
      18. 7.3.18 PLL Cascading With Internal VCO Loopback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up Modes
        1. 7.4.1.1 EEPROM Mode
        2. 7.4.1.2 ROM Mode
      2. 7.4.2 PLL Operating Modes
        1. 7.4.2.1 Free-Run Mode
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 Locked Mode
        4. 7.4.2.4 Holdover Mode
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 7.4.4.1 DCO Frequency Step Size
        2. 7.4.4.2 DCO Direct-Write Mode
      5. 7.4.5 Zero-Delay Mode (ZDM)
      6. 7.4.6 Cascaded PLL Operation
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Interface
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Interface
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map Generation
      5. 7.5.5 General Register Programming Sequence
      6. 7.5.6 EEPROM Programming Flow
        1. 7.5.6.1 EEPROM Programming Using Register Commit (Method #1)
          1. 7.5.6.1.1 Write SRAM Using Register Commit
          2. 7.5.6.1.2 Program EEPROM
        2. 7.5.6.2 EEPROM Programming Using Direct SRAM Writes (Method #2)
          1. 7.5.6.2.1 Write SRAM Using Direct Writes
      7. 7.5.7 Read SRAM
      8. 7.5.8 Read EEPROM
      9. 7.5.9 EEPROM Start-Up Mode Default Configuration
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PDN) Pin
      3. 8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.3.1 Mixing Supplies
        2. 8.1.3.2 Power-On Reset (POR) Circuit
        3. 8.1.3.3 Powering Up From a Single-Supply Rail
        4. 8.1.3.4 Power Up From Split-Supply Rails
        5. 8.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 8.1.4 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Clock Architect
      2. 9.1.2 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要なお知らせ
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Data Sheet

LMK05028 EEPROM 搭載の低ジッタ デュアルチャネル ネットワーク同期クロック

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

最新の英語版をダウンロード

1 特長

  • 2 つの独立した PLL チャネル：
    • ジッタ：150fs RMS (出力 ≥ 100MHz)
    • 位相ノイズ：–112dBc/Hz (122.88MHz 信号の 100Hz オフセット時)
    • ヒットレス スイッチング：位相キャンセレーションによる 50ps の位相過渡応答
    • プログラミング可能な Fastlock によるループ帯域幅
    • 低コストの TCXO/OCXO を使用する規格準拠の同期およびホールドオーバー
    • 任意の入力周波数から任意の出力周波数への変換
  • 4 系統のリファレンスクロック入力
    • 優先度に基づくリファレンス選択
    • 基準喪失時のデジタル ホールドオーバー
  • プログラマブル ドライバによる8つのクロック出力
    • 最大 6 種類の出力周波数に対応
    • AC-LVDS、AC-CML、AC-LVPECL、HCSL、および 1.8V か2.5V の LVCMOS 出力フォーマット
  • 起動時のカスタムクロック用 EEPROM/ROM
  • 柔軟な構成オプション
    • 入力および出力で最大 750MHz
    • XO：10～100MHz、TCXO：10～54MHz
    • DCO モード：1ppt/ステップ未満で周波数と位相の精密なステアリングを実現 (IEEE 1588スレーブ)
    • 決定性位相オフセットのゼロ遅延
    • 安定したクロック監視とステータス
    • I2Cまたは SPI インターフェイス
  • 高い電源ノイズ除去性能 (PSNR)
  • 3.3V 電源、1.8V、2.5V、または 3.3V 出力に対応
  • 産業用温度範囲：-40°C～+85°C

2 アプリケーション

  • SyncE (G.8262)、SONET/SDH (Stratum 3/3E、G.813、GR-1244、GR-253)、IEEE 1588 PTP スレーブ クロック、または光伝送ネットワーク(G.709)
  • 有線ネットワーク
    • データセンター間 / データセンター内相互接続
    • タイミングカード、ラインカード
  • データ センターおよびエンタープライズ コンピューティング
  • ブロードバンド固定回線アクセス
  • 産業用
    • 試験および測定機器
    • 医療用画像処理
  • FPGA、DSP、ASIC、CPUデバイスにおけるジッタ/ワンダ減衰、高精度周波数変換、低ジッタ クロック生成

3 概要

LMK05028は高性能のネットワーク同期クロックであり、ジッタクリーニング、クロック生成、高度なクロック監視、優れたヒットレススイッチング性能により、通信インフラおよび産業機器の厳しいタイミング要件を満たすことができます。デバイスの低ジッタおよび高 PSNR により、高速シリアルリンクにおけるビットエラーレート (BER) を低減します。

2つの PLL チャネルを備えており、150fs RMS のジッタで最大 8 つの出力クロックを生成できます。各 PLL 領域は 4 つの基準入力のいずれかを選択して、出力を同期できます。

パッケージ情報
部品番号パッケージ (1)パッケージ サイズ(2)
LMK05028RGC (VQFN、64)9.00mm × 9.00mm
(1) 詳細については、セクション 11 を参照してください。
(2) パッケージ サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます
LMK05028 概略ブロック図概略ブロック図

4 Pin Configuration and Functions

LMK05028 RGC Package 64-Pin VQFN Top ViewFigure 4-1 RGC Package 64-Pin VQFN Top View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
POWER
GNDPADGGround / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance. A 7×7 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
VDD_IN03PCore Supply (3.3 V) for Reference Inputs 0 to 3.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_IN116P
VDD_IN29P
VDD_IN34P
VDD_XO42PCore Supply (3.3 V) for XO and TCXO Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_TCXO19P
VDD_APLL149PCore Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_APLL237P
VDD_DIG8P
VDDO_021POutput Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDDO_125P
VDDO_2330P
VDDO_4550P
VDDO_659P
VDDO_763P
CORE BLOCKS
LF147AExternal Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby 0.1-µF capacitor on each pin.
LF239A
CAP_APLL148AExternal Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
CAP_APLL238A
CAP_DIG7A
INPUT BLOCKS
IN0_P1IDPLL Reference Clock Inputs 0 to 3.
Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input frequencies less than 5 MHz.
IN0_N2I
IN1_P14I
IN1_N15I
IN2_P10I
IN2_N11I
IN3_P5I
IN3_N6I
XO_P43IXO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator to lock the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P input with the N input pulled down to ground.
XO_N44I
TCXO_IN18ITCXO Input.
This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The input swing must be less than 1.3 Vpp before AC-coupling to the input pin, which has weak internal biasing of 0.6 V and no internal termination. Leave pin floating if unused.
OUTPUT BLOCKS
OUT0_P22OClock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if active or left floating if disabled through registers.
The OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. This bank is preferred for PLL2 clocks to minimize output crosstalk.
OUT0_N23O
OUT1_P27O
OUT1_N26O
OUT2_P31O
OUT2_N32O
OUT3_P34O
OUT3_N33O
OUT4_P51OClock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if active or left floating if disabled through registers.
The OUT[4:7] bank requires at least one clock from the PLL1 domain. This bank is preferred for PLL1 clocks to minimize output crosstalk.
OUT4_N52O
OUT5_P54O
OUT5_N53O
OUT6_P57O
OUT6_N58O
OUT7_P62O
OUT7_N61O
LOGIC CONTROL / STATUS (2)(3)
HW_SW_CTRL64IDevice Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR).
See Table 4-2 for start-up mode descriptions and logic pin functions.
PDN46IDevice Power-Down (active low).
When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
SDA/SDI35I/OI2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 4-2.
The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b.
SCL/SCK36II2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 4-2.
GPIO0/SYNCN45IMultifunction Inputs or Outputs.
See Table 4-2.
GPIO1/SCS24I
GPIO2/SDO60I/O
GPIO3/FINC140I
GPIO4/FDEC141I
GPIO5/FINC212I/O
GPIO6/FDEC213I/O
STATUS156I/OStatus Outputs [1:0].
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
STATUS055I/O
INSEL0_117IManual Reference Input Selection for DPLL1.
INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL0_020I
INSEL1_129IManual Reference Input Selection for DPLL2.
INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL1_028I
(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
(2) Internal resistors: PDN pin has 200-kΩ pullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-kΩ bias to VIM (approximately 0.8 V) when PDN = 0 or 400-kΩ pulldown when PDN = 1. Each INSEL pin has an 85-kΩ pullup to 1.8 V when PDN = 0 or 400-kΩ pulldown when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.

 
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