JAJSER7D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bootstrap Diode Operation
      2. 8.3.2 LDO Operation
      3. 8.3.3 Dead Time Selection
      4. 8.3.4 Overtemperature Protection
      5. 8.3.5 High-Performance Level Shifter
      6. 8.3.6 Negative HS Voltage Handling
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode Selection
        3. 9.2.2.3 Handling Ground Bounce
        4. 9.2.2.4 Independent Input Mode
        5. 9.2.2.5 Computing Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

10 Power Supply Recommendations

The power to the LMG1210 can be supplied either through the LDO or the LDO can be bypassed and 5 V can be supplied directly. The maximum input voltage to the LDO of the LMG1210 is specified in the electrical characteristics table. The minimum input voltage of the LDO is set by the minimum drop-out of the LDO at the operational current. The dropout at max current is specified in the electrical characteristics table, but a lower dropout can be used in a lower-current application. A local bypass capacitor must be placed between the VIN and VSS pins, and the VDD and VSS pins. This capacitor must be placed as close as possible to the device. TI recommends a low-ESR, ceramic, surface-mount capacitor. TI also recommends using 2 capacitors across VDD and VSS pin: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and VSS pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias requirement. The VIN and VSS capacitor can be removed if the LDO is bypassed.