JAJSER7D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bootstrap Diode Operation
      2. 8.3.2 LDO Operation
      3. 8.3.3 Dead Time Selection
      4. 8.3.4 Overtemperature Protection
      5. 8.3.5 High-Performance Level Shifter
      6. 8.3.6 Negative HS Voltage Handling
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode Selection
        3. 9.2.2.3 Handling Ground Bounce
        4. 9.2.2.4 Independent Input Mode
        5. 9.2.2.5 Computing Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

6 Pin Configuration and Functions

RVR Package
19-Pin WQFN
Top View
LMG1210 pin_diagram_snosd12.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BST 17 O Bootstrap diode anode connection point.
DHL 5 I Sets the dead time for a high-to-low transition in PWM mode by connecting a resistor to VSS. If using IIM this pin can be left floating, tied to GND, tied to VDD.
DLH 6 I Sets the dead time for a low-to-high transition in PWM mode by connecting a resistor to VSS. Tie to VDD to select IIM.
EN/HI 18 I Enable input or high-side driver control. In PWM mode this is the EN pin. In IIM mode this is the HI pin.
PWM/LI 19 I PWM input or low-side driver control. In PWM mode this is the PWM pin. In IIM mode this is the LI pin.
HB 12 I High-side driver supply. Bootstrap diode cathode connection point.
HO 10 O High-side driver output.
HS 9,13,16 I Switch node and high-side driver ground. These pins are internally connected.
LO 8 O Low-side driver output.
NC 1,11,15 — Not internally connected.
NC1 14 I For proper operation, this pin should be either unconnected or tied to HS.
Thermal Pad (HS) 21 I Connected to HS.
Thermal Pad (VSS) 20 I Connected to VSS.
VDD 4 O Low-side driver supply and LDO output. 5 V
VIN 2 I 6 V to 18 V input to LDO. If LDO is not required, connect to VDD.
VSS 3,7 — Low-side ground return: all low-side signals are referenced to this ground.