JAJSES4A February 2018 – April 2020 ADC08DJ3200
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JESD_EN | ||||||
R/W-0000 000 | R/W-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RESERVED | R/W | 0000 000 | RESERVED |
0 | JESD_EN | R/W | 1 | 0 : Disables JESD204B interface
1 : Enables JESD204B interface Before altering other JESD204B registers, JESD_EN must be cleared. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC counter is also held in reset, so SYSREF does not align the LMFC. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN. |