JAJSES4 データシート

JAJSES4A February 2018 – April 2020 ADC08DJ3200

PRODUCTION DATA.

7.10 Switching Characteristics

typical values are at T_A = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, f_IN = 248 MHz, A_IN = –1 dBFS, f_CLK = maximum-rated clock frequency, filtered 1-V_PP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DEVICE (Sampling) CLOCK (CLK+, CLK–)
t_AD	Sampling (aperture) delay from CLK± rising edge (dual-channel mode) or rising and falling edge (single-channel mode) to sampling instant	TAD_COARSE = 0x00, TAD_FINE = 0x00, and TAD_INV = 0		360		ps
t_TAD(MAX)	Maximum t_AD adjust programmable delay, not including clock inversion (TAD_INV = 0)	Coarse adjustment (TAD_COARSE = 0xFF)		289		ps
t_TAD(MAX)		Fine adjustment (TAD_FINE = 0xFF)		4.9		ps
t_TAD(STEP)	t_AD adjust programmable delay step size	Coarse adjustment (TAD_COARSE)		1.13		ps
t_TAD(STEP)	t_AD adjust programmable delay step size	Fine adjustment (TAD_FINE)		19		fs
t_AJ	Aperture jitter, rms	Minimum t_AD adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0)		50		fs
t_AJ	Aperture jitter, rms	Maximum t_AD adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0)		70⁽³⁾		fs
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
f_SERDES	Serialized output bit rate		1		12.8	Gbps
UI	Serialized output unit interval		78.125		1000	ps
t_TLH	Low-to-high transition time (differential)	20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04		37		ps
t_THL	High-to-low transition time (differential)	20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04		37		ps
DDJ	Data dependent jitter, peak-to-peak	PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2		7.8		ps
RJ	Random jitter, RMS	PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2		1.1		ps
TJ	Total jitter, peak-to-peak, with Gaussian portion defined with respect to a BER = 1e-15 (Q = 7.94)	PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 4, 5, 6, 7		28		ps
ADC CORE LATENCY
t_ADC	Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high⁽¹⁾	JMODE = 4		–4.5		t_CLK cycles
		JMODE = 5		–24.5
		JMODE = 6		–5
		JMODE = 7		–25
		JMODE = 17		–48.5
		JMODE = 18		–49
JESD204B AND SERIALIZER LATENCY
t_TX	Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe on the JESD204B serial output lane corresponding to the reference sample of t_ADC⁽²⁾	JMODE = 4	67		80	t_CLK cycles
		JMODE = 5	106		119
		JMODE = 6	67		80
		JMODE = 7	106		119
		JMODE = 17	195		208
		JMODE = 18	195		208
SERIAL PROGRAMMING INTERFACE (SDO)
t_(OZD)	Maximum delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from tri-state to valid data			7		ns
t_(ODZ)	Maximum delay from the SCS rising edge for SDO transition from valid data to tri-state			7		ns
t_(OD)	Maximum delay from the falling edge of the 16th SCLK cycle during read operation to SDO valid			12		ns

(1) t_ADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by t_TX.

(2) The values given for t_TX include deterministic and non-deterministic delays. The delay varies over process, temperature, and voltage. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.

(3) t_AJ increases because of additional attenuation on the internal clock path.

1. Only the SerDes lane DA0± is shown, but DA0± is representative of all lanes. The number of output lanes used and bit-packing format is dependent on the programmed JMODE value.

Figure 1. ADC Timing Diagram

1. The internal LMFC is assumed to be aligned with the CLK± rising edge that captures the SYSREF± high value.

2. Only SerDes lane DA0± is shown, but DA0± is representative of all lanes. All lanes output /R at approximately the same point in time. The number of lanes is dependent on the programmed JMODE value.

Figure 2. SYNCSE and TMSTP± Timing Diagram for NCO Synchronization

Figure 3. Serial Interface Timing