JAJSES4A February 2018 – April 2020 ADC08DJ3200
PRODUCTION DATA.
The ADC08DJ3200 can also be used as a single-channel ADC where the sampling rate is equal to two times the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by setting JMODE to the appropriate setting for the desired configuration as described in Table 10. Either analog input, INA± or INB±, can serve as the input to the ADC, however INA± is recommended for best performance. The analog input can be selected using SINGLE_INPUT (see the input mux control register). The digital down-converters cannot be used in single-channel mode.
NOTE
INA± is strongly recommended to be used as the input to the ADC for optimized performance in single-channel mode.