JAJSES5Q July   2006  – August 2024 TLK2711-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 TTL Input Electrical Characteristics
    6. 5.6 Transmitter/Receiver Electrical Characteristics
    7. 5.7 Reference Clock (TXCLK) Timing Requirements
    8. 5.8 TTL Output Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Transmit Interface
      2. 6.3.2  Transmit Data Bus
      3. 6.3.3  Data Transmission Latency
      4. 6.3.4  8-Bit/10-Bit Encoder
      5. 6.3.5  Pseudo-Random Bit Stream (PRBS) Generator
      6. 6.3.6  Parallel to Serial
      7. 6.3.7  High-Speed Data Output
      8. 6.3.8  Receive Interface
      9. 6.3.9  Receive Data Bus
      10. 6.3.10 Data Reception Latency
      11. 6.3.11 Serial to Parallel
      12. 6.3.12 Comma Detect and 8-Bit/10-Bit Decoding
      13. 6.3.13 LOS Detection
      14. 6.3.14 PRBS Verification
      15. 6.3.15 Reference Clock Input
      16. 6.3.16 Operating Frequency Range
      17. 6.3.17 Testability
      18. 6.3.18 Loopback Testing
      19. 6.3.19 BIST
      20. 6.3.20 Power-On Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
      2. 6.4.2 High-Speed I/O Directly-Coupled Mode
      3. 6.4.3 High-Speed I/O AC-Coupled Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Transmitter/Receiver Electrical Characteristics

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOD(p)Preemphasis VOD, direct,
VOD(p) = |VTXP – VTXN|		Rt = 50 Ω, PREM = high, DC coupled,
see Figure 5-3		6558001100mV
Rt = 50 Ω, PREM = low, DC coupled,
see Figure 5-3		5907401050
VOD(pp_p)Differential, peak-to-peak output voltage with preemphasisRt = 50 Ω, PREM = high, DC coupled,
see Figure 5-3		131016002200mVp-p
Rt = 50 Ω, PREM = low, DC coupled,
see Figure 5-3		118014802100
VOD(d)Deemphais output voltage,
|VTXP – VTXN|		Rt = 50 Ω, DC coupled, see Figure 5-3540650950mV
VOD(pp_d)Differential, peak-to-peak output voltage with deemphasisRt = 50 Ω, DC coupled, see Figure 5-3108013001900mVp-p
V(cmt)Transmit common mode voltage range, (VTXP + VTXN) / 2Rt = 50 Ω, see Figure 5-3100012501450mV
VIDReceiver input voltage differential,
|VRXP – VRXN|		See (2) 2201600mV
V(cmr)Receiver common mode voltage range, (VRXP + VRXN) / 2See (2)100012502250mV
IlkgReceiver input leakage current–1010µA
CIReceiver input capacitance4pF
Serial data total jitter (peak to peak)Differential output jitter at 2.5Gbps,
Random + deterministic, PRBS pattern		0.28UI(1)
Differential output jitter at 1.6Gbps,
Random + deterministic, PRBS pattern		0.32
tt, tfDifferential output signal rise, fall time (20% to 80%)RL = 50 Ω, CL = 5pF, see Figure 5-3150ps
Jitter tolerance eye closureDifferential input jitter, random + deterministic, PRBS pattern at zero crossing(2)0.4UI
td(Tx latency)Tx latencySee Figure 6-23438bits
td(Rx latency)Rx latencySee Figure 6-576107bits
(1) UI is the time interval of one serialized bit.
(2) Nonproduction tested parameters.