JAJSES9 February   2018 DAC8771

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DAC8771のブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. 8.3.3.1 Buck-Boost Converter Outputs
        2. 8.3.3.2 Selecting and Enabling Buck-Boost Converter
        3. 8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
          1. 8.3.3.3.1 Default Mode - CCLP[1:0] = "00"
          2. 8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01"
          3. 8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10"
          4. 8.3.3.3.4 High Side Clamp (HSCLMP)
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD bit
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. 8.4.1.1 Stand-Alone Operation
        2. 8.4.1.2 Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. 8.4.5.1 Asynchronous Mode
        2. 8.4.5.2 Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. 8.4.9.1 DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 Register Maps
        1. 8.5.1.1 DAC8771 Commands
        2. 8.5.1.2 Register Maps and Bit Functions
          1. 8.5.1.2.1  No Operation Register (address = 0x00) [reset = 0x0000]
            1. Table 6. No Operation Field Descriptions
          2. 8.5.1.2.2  Reset Register (address = 0x01) [reset = 0x0000]
            1. Table 7. Reset Register Field Descriptions
          3. 8.5.1.2.3  Reset Config Register (address = 0x02) [reset = 0x0000]
            1. Table 8. Reset Config Register Field Descriptions
          4. 8.5.1.2.4  Select DAC Register (address = 0x03) [reset = 0x0000]
            1. Table 9. Select DAC Register Field Descriptions
          5. 8.5.1.2.5  Configuration DAC Register (address = 0x04) [reset = 0x0000]
            1. Table 10. Configuration DAC Register Field Descriptions
          6. 8.5.1.2.6  DAC Data Register (address = 0x05) [reset = 0x0000]
            1. Table 11. DAC Data Register Field Descriptions
          7. 8.5.1.2.7  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
            1. Table 12. Select Buck-Boost Converter Register Field Descriptions
          8. 8.5.1.2.8  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
            1. Table 13. Configuration Buck-Boost Register Field Descriptions
          9. 8.5.1.2.9  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
            1. Table 14. DAC Channel Calibration Enable Register Field Descriptions
          10. 8.5.1.2.10 DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
            1. Table 15. DAC Channel Gain Calibration Register Field Descriptions
          11. 8.5.1.2.11 DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
            1. Table 16. DAC Channel Offset Calibration Register Field Descriptions
          12. 8.5.1.2.12 Status Register (address = 0x0B) [reset = 0x1000]
            1. Table 17. Status Register Field Descriptions
          13. 8.5.1.2.13 Status Mask Register (address = 0x0C) [reset = 0x0000]
            1. Table 18. Status Mask Register Field Descriptions
          14. 8.5.1.2.14 Alarm Action Register (address = 0x0D) [reset = 0x0000]
            1. Table 19. Alarm Action Register Field Descriptions
          15. 8.5.1.2.15 User Alarm Code Register (address = 0x0E) [reset = 0x0000]
            1. Table 20. User Alarm Code Register Field Descriptions
          16. 8.5.1.2.16 Reserved Register (address = 0x0F) [reset = N/A]
            1. Table 21. Reserved Register Field Descriptions
          17. 8.5.1.2.17 Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
            1. Table 22. Write Watchdog Timer Register Field Descriptions
          18. 8.5.1.2.18 Reserved Register (address 0x12 - 0xFF) [reset = N/A]
            1. Table 23. Reserved Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Outputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling Time with Auto-Learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8771
    2. 9.2 Typical Application
      1. 9.2.1 Single-Channel, Isolated, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.5 Electrical Characteristics

AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external, REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT OUTPUT
IOUT Output Current Ranges 0 24 mA
0 20 mA
3.5 23.5 mA
-24 24 mA
4 20 mA
ACCURACY
Resolution 16 Bits
INL Relative accuracy(1) All ranges except bipolar range -10 10 LSB
Bipolar range only -12 12 LSB
DNL Differential Nonlinearity(1) Ensured monotonic -1 1 LSB
TUE Total Unadjusted Error(1) -40°C to 125°C -0.1 0.1 %FSR
TA = +25°C -0.08 0.08
-40°C to 125°C (4-20mA) -0.130 0.130
TA = +25°C (4-20mA) -0.08 0.08
OE Offset Error(1) -40°C to 125°C -0.06 0.06 %FSR
TA = +25°C -0.05 0.05
-40°C to -125°C (4-20mA) -0.085 0.085
TA = +25°C (4-20mA) -0.04 0.04
OE-TC Offset Error Temperature Coefficient -40°C to -125°C 1.5 ppm FSR / ºC
ZCE Zero Code Error DAC data set to 0x0000 -13 13 uA
DAC data set to 0x0000 (4-20mA) -13 13 uA
ZCE-TC Zero Code Error Temperature Coefficient DAC data set to 0x0000, -40°C to -125°C 1.5 ppm/ ºC
GE Gain Error(1) -40°C to -125°C -0.1 0.1 %FSR
TA = +25°C -0.075 0.075
-40°C to -125°C (4-20mA) -0.110 0.110
TA = +25°C (4-20mA) -0.08 0.08
GE-TC Gain Error Temperature Coefficient -40C to -125C 3 ppm FSR / ºC
FSE Full Scale Error DAC data set to 0xFFFF, -40°C to -125°C -0.1 0.1 %FSR
DAC data set to 0xFFFF, -40°C to -125°C (4-20mA) -0.130 0.130 %FSR
NFSE Negative Full Scale Error DAC data set to 0x0000, bipolar range only, -40°C to -125°C -0.05 0.05 %FSR
FSE-TC Full Scale Error Temperature Coefficient 3 ppm FSR / ºC
BPZE Bipolar Zero Error bipolar range only, DAC data set to 0x8000, -40°C to -125°C -0.05 0.05 %FSR
bipolar range only, DAC data set to 0x8000, TA = +25°C -0.02 0.02
BPZE-TC Bipolar Zero Error Temperature Coefficient 0x8000h into DAC,-40°C to -125°C 4 ppm/ ºC
VCL Loop Compliance Voltage Output=24mA VPOS_IN-3 V
Output=±24mA |VNEG_IN|-3 VPOS_IN-3
RL Resistive Load All except ±24 mA range 1.2K Ω
±24 mA range 0.625K
DC-PSRR DC Power Supply Rejection Ratio DAC data set to 0x8000, 20mA range 0.1 µA/V
Zo Output Impedance DAC data set to 0x8000 10 MΩ
IOLEAK Output Current Leakage Iout is disabled or in power-down 1 nA
HART INTERFACE
VHART-IN HART Input 400 500 600 mVpp
Corresponding Output HART In = 500mVpp 1.2KHz 1 mApp
VOLTAGE OUTPUT
VOUT Voltage Output Ranges (normal mode) 0 5
0 10
-5 5
-10 10
Voltage Output Ranges (Overrange mode) 0 6
0 12
-6 6
-12 12
ACCURACY
Resolution 16 Bits
INL Relative Accuracy, INL(1) -12 12 LSB
DNL Differential Nonlinearity, DNL(1) Ensured monotonic -1 1 LSB
TUE Total Unadjusted Error, TUE(1) -40°C to 125°C, VOUT unloaded -0.1 ±0.05 0.1 %FSR
TA = +25°C, VOUT unloaded -0.75 0.75
BPZE Bipolar Zero Error bipolar range only, DAC data set to 0x8000, -40°C to 125°C, VOUT unloaded -0.05 0.05 %FSR
bipolar range only, DAC data set to 0x8000, TA = +25°C, VOUT unloaded -0.03 0.03
BPZE-TC Bipolar Zero Error Temperature Coefficient bipolar range only, DAC data set to 0x8000, -40°C to 125°C, (VOUT unloaded) 1 ppm FSR / ºC
OE Offset Error Unipolar ranges only, (Vout unloaded), -40°C to 125°C -5 5 mV
OE Offset Error Unipolar ranges only, (Vout unloaded), TA = 25°C 0.65 mV
OE-TC Offset Error Temperature Coefficient Unipolar ranges only, -40°C to 125°C 1.5 ppm FSR/ ºC
GE Gain Error(1) -40°C to 125°C, VOUT unloaded -0.1 0.1 %FSR
TA = +25°C, VOUT unloaded -0.07 0.07
GE-TC Gain Error Temperature Coefficient 3 ppm FSR / ºC
FSE Full Scale Error DAC data set to 0xFFFF, -40° to 125°C, (Vout unloaded) -0.1 0.1 %FSR
DAC data set to 0xFFFF, 25°C, (Vout unloaded) 0.03 %FSR
NFSE Negative Full Scale Error Bipolar ranges only, DAC data set to 0x0000, -40°C to 125°C, (Vout unloaded) -0.07 0.07 %FSR
Bipolar ranges only, DAC data set to 0x0000, -40°C to 125°C, (Vout unloaded) 0.002 %FSR
FSE-TC Full Scale Error Temperature Coefficient (Vout unloaded) 2 ppm FSR / ºC
Headroom Output unloaded, VPOS_IN with respect to VOUT, DAC data set to 0xFFFF, specified by design 0.5 V
1kΩ output load, VPOS_IN with respect to VOUT, DAC data set to 0xFFFF, specified by design 3 V
Footroom Bipolar, ranges only, VNEG_IN with respect to VOUT, DAC data set to 0x0000, specified by design -3 V
Unipolar ranges only, VNEG_IN with respect to VOUT, DAC data set to 0x0000, specified by design -5 V
Short-Circuit Current SCLIM[1:0] = "00" (see register map) 17 27 mA
SCLIM[1:0] = "01" (see register map) 8 12 mA
SCLIM[1:0] = "10" (see register map) 22 30 mA
SCLIM[1:0] = "11" (see register map) 26 36 mA
RL Load 1 kΩ
CL Capacitive Load Stability RL = Open 20 nF
RL = 1 kΩ 20 nF
RL = 1 kΩ with External compensation capacitor (150pF) connected. 1 µF
ZO DC Output Impedance Voltage output enabled, Vout = Mid-Scale, 0-10V range 0.01 Ω
Voltage output disabled 50 MΩ
Voltage output disabled (POC = '0') 30 kΩ
DC-PSRR DC Power Supply Rejection Ratio No Output Load 10 µV/V
VSENSEP Impedance VOUT Enabled, Vout = Mid-Scale, 0-10V Range, specified by design 120 kΩ
VSENSEN Impedance VOUT Enabled, Vout = Mid-Scale, 0-10V Range, specified by design 240 kΩ
EXTERNAL REFERENCE INPUT
IREF External reference current Vout = Negative Full-Scale, ±12V range 350 µA
Reference Input Capacitance 100 pF
INTERNAL REFERENCE OUTPUT
VREF Reference Output TA = 25°C 4.99 5.01 V
VREF-TC Reference TC TA = -40°C to 125°C -10 10 ppm/°C
TUE DAC Voltage Output Total unadjusted error(1) -40°C to 125°C, VOUT unloaded, Internal reference enabled 0.2 %FSR
DAC Current Output Total unadjusted error(1) -40°C to +125°C, Internal reference enabled 0.2 %FSR
Output Noise (0.1 Hz to 10 Hz) TA = 25°C 13 µV p-p
Noise Spectral Density At 10 kHz, 25°C 200 nV/sqrtHz
CL Capacitive Load 600 nF
IL Load Current ±5 mA
Short Circuit Current Reference output shorted to GND 20 mA
Load Regulation Sourcing and Sinking, TA = +25°C 5 µV/mA
Line regulation TA = +25°C 1 uV/V
BUCK BOOST CONVERTER
RON Switch On Resistanvce TA = +25°C 3 Ω
ILEAK Switch Leakage Current TA = +25°C 20 nA
L Inductor between LP and LN 100 µH
ILMAX Peak Inductor Current TA = +25°C, maximum specified by design 0.35 0.5 A
VO Output Voltage VPOS_IN 4 32 V
VNEG_IN -18 -5 V
CL Load Capacitor VPOS_IN and VNEG_IN 10 µF
Start up time After enabling VPOS_IN and VNEG_IN with 10µF load capacitor on these pins 3 ms
DVDD LDO
VO Output Voltage 5 V
ILOAD Load Current 10 mA
CL Load Capacitor 0.2 µF
THERMAL ALARM
Trip point 150 °C
Hysteresis 15 °C
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input Current -5 5 µA
Pin Capacitance Per pin 10 pF
DIGITAL OUTPUTS
SDO
VOL Output Low Voltage Sinking 200 µA 0.4 V
VOH Output High Voltage Sourcing 200 µA DVDD-0.5 V
ILEAK High Impedance Leakage -5 5 µA
High Impedance Output Capacitance 10 pF
ALARM
VOL Output Low Voltage At 10 mA 0.4 V
ILEAK High Impedance Leakage 50 µA
High Impedance Output Capacitance 10 pF
POWER REQUIREMENTS
IAVDD Current Flowing into AVDD Buck-Boost converter enabled, All IOUT Active, 0mA, 0-20mA range 3 mA
IOUT Active, 0 mA, 0-20mA range, VNEG_IN = 0V 1.3 mA
IPVDD Current Flowing into PVDD Buck-Boost converter enabled, Peak Current, specified by design 0.5 A
Buck-Boost converter disabled 0.1 mA
IDVDD Current Flowing into DVDD All digital pins at DVDD, DVDD 2.7V to 5.5V 1.8 mA
IVPOS_IN Current Flowing into VPOS_IN IOUT Active, 0mA, 0-20mA range 1.2 mA
VOUT Active, no load, 0-10V range, mid scale code 3 mA
IVNEG_IN Current Flowing into VNEG_IN IOUT Active, 0mA, ±24mA range 1.2 mA
VOUT Active, no load, 0-10V range, mid scale code 3 mA
PDISS Power dissipation (PVDD+AVDD) Buck-Boost converter positive output enabled, IOUT mode operation, All IOUT channels enabled, Rload = 1Ω, 24mA, PVDD = AVDD = 12V 0.226 0.275 W
IVSENSEP Current Flowing into VSENSEP VOUT Disabled, specified by design 40 nA
IVSENSEN Current Flowing into VSENSEN VOUT Disabled, specified by design 20 nA
DYNAMIC PERFORMANCE
VOLTAGE OUTPUT
Tsett Output Voltage Settling Time 0 to 10V, to ±0.03% FSR RL = 1kΩ || CL = 200pF 15 µs
0 to 5V, to ±0.03% FSR RL = 1kΩ || CL = 200pF 10 µs
-5 to 5V, to ±0.03% FSR RL = 1kΩ || CL = 200pF 20 µs
-10 to 10V, to ±0.03% FSR RL = 1kΩ || CL = 200pF 30 µs
Output voltage ripple Buck-Boost converter enabled, 50 KHz 20dB/decade low-pass filter on VPOS_IN 2 mVpp
SR Slew Rate RL = 1kΩ || CL = 200pF 1 V/µs
Power-On Glitch Energy(2) Specified by design 0.1 V
Power-off Glitch Energy(3) Specified by design 0.8 V
Code-Code Glitch 0.15 µV-sec
Digital Feedthrough 1 nV-sec
Output Noise (0.1 Hz to 10 Hz Bandwidth) 0-10V range, Mid-Scale 0.1 LSB p-p
Output Noise (100 kHz Bandwidth) 0-10V range, Mid-Scale 200 µVrms
Output Noise Spectral Density ±10V Measured at 10 kHz, Mid-Scale 200 nV/sqrtHz
AC-PSRR AC Power Supply Rejection Ratio 200mV 50/60Hz sinusoid superimposed on power supply voltage (AC analysis). -75 dB
CURRENT OUTPUT
Tsett Output Current Settling Time 24 mA Step, to 0.1% FSR, no L 10 µs
24 mA Step, to 0.1% FSR , L = 1mH, CL = 22nF 50 µs
Output current ripple Buck-boost converter enabled, 50 KHz 20dB/decade low-pass filter on VPOS_IN 2 µApp
L Inductive Load(4) 50 mH
AC-PSRR AC Power Supply Rejection Ratio 200mV 50/60Hz Sine wave superimposed on power supply voltage -75 dB
(1) For current output all ranges except ±24 mA, low code of 256d and a high code of 65280d are used, for ±24 mA range low code of 0d and a high code of 65280d. For voltage output, low code of 256d and a high code of 65280d are used
(2) No load, DVDD supply ramps up before VPOS_IN, and VNEG_IN, ramp rate of VPOS_IN,and VNEG_IN limited to 18V/msec
(3) Vout disabled, no load, ramp rate of VPOS_IN, and VNEG_IN limited to 18V/msec
(4) 680nF is required at IOUT pin for 50mH pure inductor load