JAJSES9 February 2018 DAC8771
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | Reserved | Reserved | Reserved | CLSLA | Reserved | ||
R/W | R/W | R/W | R/W | R/W | R/W | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | CHA | DSDO | CREN | WPD[1:0] | WEN | |
R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | Reserved | R/W | 000 | Reserved |
9 | CLSLA | R/W | 0 | Clear Select
0 - DAC registers cleared to zero scale upon hardware or software clear (default) 1 - DAC registers cleared to mid scale upon hardware or software clear |
8:6 | Reserved | R/W | 0 | Reserved |
5 | CHA | R/W | 0 | Channel A selected |
4 | DSDO | R/W | 0 | Disable SDO - When set, this bit disables daisy chain operation and SDO pin is set to HiZ, enabled by default |
3 | CREN | R/W | 0 | Enable CRC - When set, this bit enables frame error checking, disabled by default |
2:1 | WPD[1:0] | R/W | 00 | Watchdog Timer Period
00 - 10 ms (typical) 01 - 51 ms (typical) 10 - 102 ms (typical) 11 - 204 ms (typical) |
0 | WEN | R/W | 0 | Enable Watchdog Timer - When set, this bit enables watchdog timer, disabled by default |