JAJSET7C May   2017  – October 2018 IWR1443

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1  Power Supply Sequencing and Reset Timing
      2. 5.9.2  Synchronized Frame Triggering
      3. 5.9.3  Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
        2. 5.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.9.4.3 SPI Slave Mode I/O Timings
          1. Table 5-11 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5  LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6  General-Purpose Input/Output
        1. Table 5-13 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7  Controller Area Network Interface (DCAN)
        1. Table 5-14 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 5.9.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.9.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.9.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.9.11 JTAG Interface
        1. Table 5-20 JTAG Timing Conditions
        2. Table 5-21 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-22 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
      12. 5.9.12 Camera Serial Interface (CSI)
        1. Table 5-23 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 External Interfaces
    4. 6.4 Subsystems
      1. 6.4.1 RF and Analog Subsystem
        1. 6.4.1.1 Clock Subsystem
        2. 6.4.1.2 Transmit Subsystem
        3. 6.4.1.3 Receive Subsystem
        4. 6.4.1.4 Radio Processor Subsystem
      2. 6.4.2 Master (Control) System
      3. 6.4.3 Host Interface
    5. 6.5 Accelerators and Coprocessors
    6. 6.6 Other Subsystems
      1. 6.6.1 A2D Data Format Over CSI2 Interface
      2. 6.6.2 ADC Channels (Service) for User Application
        1. Table 6-2 GP-ADC Parameter
    7. 6.7 Identification
    8. 6.8 Boot Modes
      1. 6.8.1 Flashing Mode
      2. 6.8.2 Functional Mode
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Table 5-23 CSI Switching Characteristics

over operating Tj temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
HPTX
HSTXDBR Data bit rate (1 or 2 data lane PHY) 150 600 Mbps
(4 data lane PHY) 150 600
fCLK DDR clock frequency (1 or 2 data lane PHY) 75 450 MHz
(4 data lane PHY) 75 300
ΔVCMTX(LF) Common-level variation from 75 to 450 MHz of CSI2 clock frequency –50 50 mVpeak
tR and tF 20% to 80% rise time and fall time 150 ns
0.3 UI
LPTX DRIVER
tRLP and tFLP 15% to 85% rise time and fall time 25 ns
tEOT(1) Time from start of THS-TRAIL period to start of LP-11 state 105 + 12*UI ns
δV/δtSR(2)(3)(4) Slew rate. CLOAD = 0 to 5 pF 500 mV/ns
Slew rate. CLOAD = 5 to 20 pF 200
Slew rate. CLOAD = 20 to 70 pF 100
CLOAD(2) Load capacitance 0 70 pF
DATA-CLOCK Timing Specification
UINOM Nominal Unit Interval (1, 2, or 3 data lane PHY) 1.11 13.33 ns
Nominal Unit Interval (4 data lane PHY) 1.67 13.33
UIINST,MIN Minimum instantaneous Unit Interval (1, 2, or 3 data lane PHY) 1.033 0.975*UINOM – 0.05 ns
Minimum instantaneous Unit Interval (4 data lane PHY) 1.131
TSKEW[TX] Data to clock skew measured at transmitter –0.15 0.15 UIINST,MIN
CSI2 TIMING SPECIFICATION
TCLK-MISS Time-out for receiver to detect absence of clock transitions and disable the clock lane HS-RX. 60 ns
TCLK-POST Time that the transmitter continues to send HS clock after the last associated data lane has transitioned to lp mode. Interval is defined as the period from the end of THS-TRAIL to the beginning of TCLK-TRAIL. 60 ns + 52*UI ns
TCLK-PRE Time that the HS clock shall be driven by the transmitter before any associated data lane beginning the transition from LP to HS mode. 8 ns
TCLK-PREPARE Time that the transmitter drives the clock lane LP-00 line state immediately before the HS-0 line state starting the HS transmission. 38 95 ns
TCLK-TERM-EN Time for the clock lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX. Time for Dn to reach VTERM-EN 38 ns
TCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 60 ns
TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state before starting the clock. 300 ns
TD-TERM-EN Time for the data lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX. Time for Dn to reach VTERM-EN 35 ns + 4*UI ns
TEOT Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL, to the start of the LP-11 state following a HS burst. 105 ns + n*12*UI ns
THS-PREPARE Time that the transmitter drives the data lane LP-00 line state immediately before the HS-0 line state starting the HS transmission 40 + 4*UI 85 + 6*UI ns
THS-PREPARE + THS-ZERO THS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns
THS-SKIP Time interval during which the HS-RX should ignore any transitions on the data lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 40 55 ns + 4*UI ns
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns
THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst max(n*8*UI, 60 ns + n*4*UI)(5)(6) ns
TLPX Transmitted length of any low-power state period 50(7) ns
(1) With an additional load capacitance CCM of 0 to 60 pF on the termination center tap at RX side of the lane
(2) While driving CLOAD. Load capacitance includes 50 pF of transmission line capacitance, and 10 pF each for TX and RX.
(3) When the output voltage is from 15% to 85% of the fully settled LP signal levels
(4) Measured as average across any 50 mV segment of the output signal transition
(5) If a > b then max(a, b) = a, otherwise max(a, b) = b.
(6) Where n = 1 for Forward-direction HS mode and n = 4 for Reverse-direction HS mode
(7) TLPX is an internal state machine timing reference. Externally measured values may differ slightly from the specified values due to asymmetrical rise and fall times.
IWR1443 clock_and_data_timing.gifFigure 5-18 Clock and Data Timing in HS Transmission
IWR1443 30188403.gifFigure 5-19 High-Speed Data Transmission Burst
IWR1443 clock_lane_switching.gif
1. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 5-20 Switching the Clock Lane Between Clock Transmission and Low-Power Mode