JAJSEW3C may 2017 – january 2022 AWR1443
PRODUCTION DATA
The AWR1443 supports seven differential LVDS IOs/Lanes. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M), and one HS_DEBUG LVDS pair. The LVDS interface is used for debugging. The LVDS interface supports the following data rates:
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.