JAJSEW3C may   2017  – january 2022 AWR1443

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

8.9.9.1 I2C Timing Requirements(1)

STANDARD MODEFAST MODEUNIT
MINMAXMINMAX
tc(SCL)Cycle time, SCL102.5μs
tsu(SCLH-SDAL)Setup time, SCL high before SDA low
(for a repeated START condition)		4.70.6μs
th(SCLL-SDAL)Hold time, SCL low after SDA low
(for a START and a repeated START condition)		40.6μs
tw(SCLL)Pulse duration, SCL low4.71.3μs
tw(SCLH)Pulse duration, SCL high40.6μs
tsu(SDA-SCLH)Setup time, SDA valid before SCL high250100μs
th(SCLL-SDA)Hold time, SDA valid after SCL low03.45(1)00.9μs
tw(SDAH)Pulse duration, SDA high between STOP and START conditions4.71.3μs
tsu(SCLH-SDAH)Setup time, SCL high before SDA high
(for STOP condition)		40.6μs
tw(SP)Pulse duration, spike (must be suppressed)050ns
Cb(2)(3)Capacitive load for each bus line400400pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
GUID-3653C253-8E5C-454D-BA01-0F324267D1DB-low.gifFigure 8-14 I2C Timing Diagram
Note:
  • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  • The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).