JAJSEW3C may   2017  – january 2022 AWR1443

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

7.3 Pin Multiplexing

Table 7-1 Pin Multiplexing
REGISTER ADDRESS(1)PIN NAMEPINDIGITAL PIN MUX CONFIG VALUE [Bits3:0]FUNCTIONPAD STATE
nReset = 0 [ASSERTED]
SIGNAL NAMESIGNAL DESCRIPTIONSIGNAL TYPESTATEINTERNAL WEAK PULL STATE
EA00hGPIO_12P60GPIO_12General Purpose IOIOHi-ZWeak Pull Down
1SPI_HOST1_INTRGeneral Purpose IO [AWR14xx]O
EA04hGPIO_0N40GPIO_13General Purpose IOIOHi-ZWeak Pull Down
1GPIO_0General Purpose IOIO
2PMIC_CLKOUTDithered Clock Output for PMICO
EA08hGPIO_1N70GPIO_16General Purpose IOIOHi-ZWeak Pull Down
1GPIO_1General Purpose IOIO
2SYNC_OUTLow Frequency Synchronization Signal outputO
EA0ChMOSI_1R80GPIO_19General Purpose IOIOHi-ZWeak Pull Up
1MOSI_1SPI Channel#1 Data InputIO
2CAN_RXCAN InterfaceI
EA10hMISO_1P50GPIO_20General Purpose IOIOHi-ZWeak Pull Up
1MISO_1SPI Channel#1 Data OutputIO
2CAN_TXCAN InterfaceO
EA14hSPI_CLK_1R90GPIO_3General Purpose IOIOHi-ZWeak Pull Up
1SPI_CLK_1SPI Channel#1 ClockIO
RCOSC_CLKO
EA18hSPI_CS_1R70GPIO_30General Purpose IOIOHi-ZWeak Pull Up
1SPI_CS_1SPI Channel#1 Chip SelectIO
RCOSC_CLKO
EA1ChMOSI_2R30GPIO_21General Purpose IOIOHi-Z
1MOSI_2SPI Channel#2 Data InputIO
2I2C_SDAI2C DataIO
EA20hMISO_2P40GPIO_22General Purpose IOIOHi-Z
1MISO_2SPI Channel#2 Data OutputIO
2I2C_SCLI2C ClockIO
EA24hSPI_CLK_2R50GPIO_5General Purpose IOIOHi-Z
1SPI_CLK_2SPI Channel#2 ClockIO
MSS_UARTA_RXIO
6MSS_UARTB_TXDebug: Firmware TraceO
7BSS_UART_TXDebug: Firmware TraceO
EA28hSPI_CS_2R40GPIO_4General Purpose IOIOHi-Z
1SPI_CS_2SPI Channel#2 Chip SelectIO
MSS_UARTA_TXIO
6MSS_UARTB_TXDebug: Firmware TraceO
7BSS_UART_TXDebug: Firmware TraceO
EA2ChQSPI[0]R110GPIO_8General Purpose IOIOHi-ZWeak Pull Down
1QSPI[0]QSPI Data IN/OUTIO
2MISO_2SPI Channel#1 Data OutputIO
EA30hQSPI[1]P90GPIO_9General Purpose IOIOHi-ZWeak Pull Down
1QSPI[1]QSPI Data IN/OUTIO
2MOSI_2SPI Channel#2 Data InputIO
EA34hQSPI[2]R120GPIO_10General Purpose IOIOHi-ZWeak Pull Down
1QSPI[2]QSPI Data IN/OUTIO
EA38hQSPI[3]P100GPIO_11General Purpose IOIOHi-ZWeak Pull Down
1QSPI[3]QSPI Data IN/OUTI
EA3ChQSPI_CLKR100GPIO_7General Purpose IOIOHi-ZWeak Pull Down
1QSPI_CLKQSPI Clock output from the device.
Device operates as a master with the serial flash being a slave		O
2SPI_CLK_2SPI Channel#2 ClockIO
EA40hQSPI_CSP80GPIO_6General Purpose IOIOHi-ZWeak Pull Up
1QSPI_CSQSPI Chip Select output from the device.
Device operates as a master with the serial flash being a slave		O
2SPI_CS_2SPI Channel#2 Chip SelectIO
NERROR_INP7NERROR_INFailsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by FirmwareIHi-Z
WARM_RESETN12WARM_RESETOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.IOHi-Z InputOpen Drain
NERROR_OUTN8NERROR_OUTOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.OHi-ZOpen Drain
EA50hTCKM130GPIO_17General Purpose IOIOHi-ZWeak Pull Down
1TCKJTAG ClockI
2MSS_UARTB_TXDebug: Firmware TraceO
6BSS_UART_RXDebug: Firmware TraceI
EA54hTMSL130GPIO_18General Purpose IOIOHi-ZWeak Pull Up
1TMSJTAG Test Mode SelectIO
2BSS_UART_TXDebug: Firmware TraceO
EA58hTDIH130GPIO_23General Purpose IOIOHi-ZWeak Pull Up
1TDIJTAG Test Data InI
MSS_UARTA_RXIO
EA5ChTDOJ130GPIO_24General Purpose IOIOHi-Z
1TDOJTAG Test Data OutO
MSS_UARTA_TXIO
6MSS_UARTB_TXDebug: Firmware TraceO
7BSS_UART_TXDebug: Firmware TraceO
SOP0Sense On Power [Reset] Line
Impacts boot mode		I
EA60hMCU_CLKOUTN90GPIO_25General Purpose IOIOHi-ZWeak Pull Down
1MCU_CLKOUTProgrammable clock given out to external MCU or the processorO
10BSS_UART_RXDebug: Firmware TraceI
EA64hGPIO_2N130GPIO_26General Purpose IOIOHi-ZWeak Pull Down
1GPIO_2General Purpose IOIO
7MSS_UARTB_TXDebug: Firmware TraceO
8BSS_UART_TXDebug: Firmware TraceO
9SYNC_OUTLow frequency Synchronization signal outputO
10PMIC_CLKOUTDithered clock input to PMICO
EA68hPMIC_CLKOUTP130GPIO_27General Purpose IOIOHi-ZWeak Pull Down
1PMIC_CLKOUTDithered Clock Output for PMICO
SOP2Sense On Power [Reset] Line
Impacts boot mode		I
EA6ChSYNC_INN100GPIO_28General Purpose IOIOHi-ZWeak Pull Down
1SYNC_INLow frequency Synchronization signal inputI
6MSS_UARTB_RXDebug: Firmware TraceI
EA70hSYNC_OUTP110GPIO_29General Purpose IOIOHi-ZWeak Pull Down
1SYNC_OUTLow frequency Synchronization signal outputO
RCOSC_CLKO
SOP1Sense On Power [Reset] Line
Impacts boot mode		I
EA74hRS232_RXN50GPIO_15General Purpose IOIOHi-ZWeak Pull Up
1RS232_RXDebug: Firmware load to RAMIO
2MSS_UARTA_RXFLASH Programming
Bootloader Controlled		I
6BSS_UART_TXDebug: Firmware TraceO
7MSS_UARTB_RXDebug: Firmware TraceI
EA78hRS232_TXN60GPIO_14General Purpose IOIO
1RS232_TXDebug: Firmware load to RAMIO
5MSS_UARTA_TXFLASH Programming
Bootloader Controlled		O
6MSS_UARTB_TXDebug: Firmware TraceO
7BSS_UART_TXDebug: Firmware TraceO
(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.