JAJSEW3C
may 2017 – january 2022
AWR1443
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
説明
4
機能ブロック図
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Signal Descriptions
7.2.1
Signal Descriptions
7.3
Pin Multiplexing
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Power Supply Specifications
8.6
Power Consumption Summary
8.7
RF Specification
8.8
Thermal Resistance Characteristics for FCBGA Package [ABL0161]
8.9
Timing and Switching Characteristics
8.9.1
Power Supply Sequencing and Reset Timing
8.9.2
Synchronized Frame Triggering
8.9.3
Input Clocks and Oscillators
8.9.3.1
Clock Specifications
8.9.4
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.9.4.1
Peripheral Description
8.9.4.2
MibSPI Transmit and Receive RAM Organization
8.9.4.2.1
SPI Timing Conditions
8.9.4.2.2
SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
8.9.4.2.3
SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
8.9.4.3
SPI Peripheral Mode I/O Timings
8.9.4.3.1
SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
8.9.4.4
Typical Interface Protocol Diagram (Peripheral Mode)
8.9.5
LVDS Interface Configuration
8.9.5.1
LVDS Interface Timings
8.9.6
General-Purpose Input/Output
8.9.6.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
8.9.7
Controller Area Network Interface (DCAN)
8.9.7.1
Dynamic Characteristics for the DCANx TX and RX Pins
8.9.8
Serial Communication Interface (SCI)
8.9.8.1
SCI Timing Requirements
8.9.9
Inter-Integrated Circuit Interface (I2C)
8.9.9.1
I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
8.9.10
Quad Serial Peripheral Interface (QSPI)
8.9.10.1
QSPI Timing Conditions
8.9.10.2
Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
8.9.10.3
QSPI Switching Characteristics
8.9.11
JTAG Interface
8.9.11.1
JTAG Timing Conditions
8.9.11.2
Timing Requirements for IEEE 1149.1 JTAG
8.9.11.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
External Interfaces
9.4
Subsystems
9.4.1
RF and Analog Subsystem
9.4.1.1
Clock Subsystem
9.4.1.2
Transmit Subsystem
9.4.1.3
Receive Subsystem
9.4.1.4
Radio Processor Subsystem
9.4.2
Main (Control) System
9.4.3
Host Interface
9.5
Accelerators and Coprocessors
9.6
Other Subsystems
9.6.1
ADC Channels (Service) for User Application
9.6.1.1
GP-ADC Parameter
9.7
Boot Modes
9.7.1
Flashing Mode
9.7.2
Functional Mode
10
Applications, Implementation, and Layout
10.1
Application Information
10.2
Short-Range Radar
10.3
Blind Spot Detector and Ultrasonic Upgrades
10.4
Reference Schematic
11
Device and Documentation Support
11.1
Device Nomenclature
11.2
Tools and Software
11.3
Documentation Support
11.4
サポート・リソース
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
用語集
12
Mechanical, Packaging, and Orderable Information
12.1
Packaging Information
8
Specifications