JAJSEZ9L march   2018  – august 2023 BQ77915

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

9.3.8 State Comparator

A small, low-offset analog state comparator monitors the sense resistor voltage (SRP–SRN) to determine when the pack is in a DISCHARGE state less than a minimum threshold, VSTATE_D, or a CHARGE state greater than a maximum threshold, VSTATE_C. The state comparator turns on the CHG FET to prevent damage or overheating during discharge in fault states that call for having only the CHG FET off. This is vice versa for the DSG FET during charging in fault that call for having only the DSG FET off. Also, the state comparator is turned on in NORMAL mode (CHG and DSG FETs on) during cell balancing so that cell balancing is performed only when the pack is charging.

Table 9-6 summarizes when the state comparator is operational. The state comparator is on only during faults detected that call for only one FET to be turned off, and in NORMAL mode during cell balancing so that cell balancing is performed only when the pack is charging.

Table 9-6 State Comparator Operation Summary in Fault Conditions
MODECHGDSGSTATE COMP
NORMAL mode, no cell balancingONONOFF
NORMAL mode, cell balancingONONVSTATE_C detection
UV, CTRDONOFFVSTATE_C detection
OV, UTC, OTC, CTRCOFFONVSTATE_D detection
OCD1, OCD2, SCD, OCC, UTD, OTD, OWOFFOFFOFF
GUID-2CEDC056-CC5A-4C37-A702-6BEC7D7D3470-low.gifFigure 9-7 State Comparator Thresholds

Any time a CHG fault is present and a DSG fault is not present, the device enables the state comparator. If the pack is in a fault state where charging is prohibited but discharging is permitted (OV, OTC, UTC, and CTRC), a discharge is possible. When this happens, the CHG FET driver is turned on to avoid damage, as it otherwise carries the discharge current through its body diode. The state comparator (with the VSTATE_D threshold and VSTATE_D_HYS hysteresis) remains on for the entire duration of a CHG fault with no DSG fault event.

If there is a DSG fault under CTRD conditions, the DSG FET is turned on if charge is detected. The state comparator (with VSTATE_C threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault event.