Design all traces for matched impedance. The single-ended RF trace must be controlled for 50-Ω impedance, while the differential OSCIN, LO, and IF traces must be controlled for 100-Ω differential impedance.
Run an uninterrupted ground plane beneath all impedance-controlled traces. No other currents should flow directly under the controlled impedance traces.
Keep high-frequency traces as short as possible to minimize losses, or potential for cross-coupling.
Controlled impedance can be challenging in materials not designed for RF applications. For example, standard FR-4 has a wide range of acceptable dielectric constants in practice. Although the constants seen in boards from the same panel or material lot code may match very well, this does not ensure that the constants match between different lots or different dielectric manufacturers. Furthermore, FR-4 has a high loss tangent compared to many other materials, which can result in much greater attenuation of high frequency signals across the same distances. TI recommends the use of materials designed specifically for high-frequency use, such as RO4350B or RO4003C from Rogers Corporation.
The RF pin is surrounded on three sides by ground pins to assist in the creation of a coplanar waveguide structure. Design the coplanar waveguide to minimize current flow on the ground traces around the pins.
The IF outputs are low impedance, and require resistors to set the output impedance.
The LO pins are capacitively coupled as inputs, with internal 50-Ω termination. Use 50-Ω pullup resistors to VCC_BUF to bias these pins as inputs, if driven through external capacitors. The LO pins require 50-Ω pullup resistors to VCC_BUF as outputs.
The LO pins are located very close to the Q-channel IF pins, and the LO buffer supply is located between these two ports. Placing a bypass capacitor as close as possible to the LO buffer is recommended for proper operation, but this presents a potential problem: vias to VCC and GND must be routed between the differential pairs. Because the high frequency currents in the bypass capacitor and the LO buffer circuit tend to follow the loop with the lowest inductance, and since the VCC via interrupts the path from capacitor ground to IC ground on the plane layer immediately below the top, ground currents tend to travel around this via, in the path of the LO and IF coupling to the plane layer. To maintain the signal integrity of both the LO and IF differential traces, no other currents should be flowing immediately below them on the plane layer. Therefore, the LO bypass capacitor ground via must not connect to the plane layer immediately below the capacitor. TI recommends connecting through the subsequent layer. See the Layout Example section on how this is done.