JAJSF23B March   2018  – July 2018 INA1620

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      INA1620の簡略化された内部回路図
      2.      FFT: 1kHz、32Ω負荷、50mW
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Matched Thin-Film Resistor Pairs
      2. 7.3.2 Power Dissipation
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 EN Pin
      5. 7.3.5 GND Pin
      6. 7.3.6 Input Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Output Transients During Power Up and Power Down
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
      2. 8.1.2 Resistor Tolerance
      3. 8.1.3 EMI Rejection
      4. 8.1.4 EMIRR +IN Test Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Other Application Examples
      1. 8.3.1 Preamplifier for Professional Microphones
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

RTW Package
24-Pin QFN
Top View
INA1620 SBOS859_D002.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 3 — Connect to ground
EN 16 I Shutdown (logic low), enable (logic high)
IN+ A 22 I Noninverting input, channel A
IN- A 21 I Inverting input, channel A
IN+ B 9 I Noninverting input, channel B
IN- B 10 I Inverting input, channel B
NC 4 — No internal connection
NC 15 — No internal connection
OUT A 17 O Output, channel A
OUT B 14 O Output, channel B
R1A 24 — Resistor pair 1, end point A
R1B 23 — Resistor pair 1, center point
R1C 1 — Resistor pair 1, end point C
R2A 19 — Resistor pair 2, end point A
R2B 20 — Resistor pair 2, center point
R2C 18 — Resistor pair 2, end point C
R3A 12 — Resistor pair 3, end point A
R3B 11 — Resistor pair 3, center point
R3C 13 — Resistor pair 3, end point C
R4A 7 — Resistor pair 4, end point A
R4B 8 — Resistor pair 4, center point
R4C 6 — Resistor pair 4, end point C
V+ 2 — Positive (highest) power supply
V– 5 — Negative (lowest) power supply
Thermal pad Exposed thermal die pad on underside; connect thermal die pad to V–.