JAJSF47A April   2018  – May 2018 UCC28742

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      10W、5VのAC/DCコンバータの標準的な効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 FB (Feedback)
      2. 7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      3. 7.3.3 Control Law
      4. 7.3.4 Constant Current Limit and Delayed Shutdown
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
      7. 7.3.7 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  VDD Capacitance, CDD
        3. 8.2.2.3  VDD Start-Up Resistance, RSTR
        4. 8.2.2.4  Input Bulk Capacitance and Minimum Bulk Voltage
        5. 8.2.2.5  Transformer Turns Ratio, Inductance, Primary-Peak Current
        6. 8.2.2.6  Transformer Parameter Verification
        7. 8.2.2.7  VS Resistor Divider and Line Compensation
        8. 8.2.2.8  Standby Power Estimate
        9. 8.2.2.9  Output Capacitance
        10. 8.2.2.10 Feedback Loop Design Consideration
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1  容量項(ファラッド単位)
        2. 11.1.2.2  デューティ・サイクル項
        3. 11.1.2.3  周波数項(ヘルツ単位)
        4. 11.1.2.4  電流項(アンペア単位)
        5. 11.1.2.5  電流および電圧のスケーリング項
        6. 11.1.2.6  変圧器の項
        7. 11.1.2.7  電力項(ワット単位)
        8. 11.1.2.8  抵抗項(オーム単位)
        9. 11.1.2.9  タイミング項(秒単位)
        10. 11.1.2.10 電圧項(ボルト単位)
        11. 11.1.2.11 AC電圧項(VRMS単位)
        12. 11.1.2.12 効率項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

7.3.1.3 VS (Voltage-Sense)

The VS pin connects to a resistor-divider from the auxiliary winding to ground. The auxiliary voltage waveform is sampled at the end of the transformer secondary-current demagnetization time. The waveform on the VS pin determines (1) the timing information to achieve valley-switching, (2) the timing to control the duty-cycle of the transformer secondary current, and (3) the output voltage over-voltage. Avoid placing a filter capacitor on this input which interferes with accurate sensing of this waveform.

Besides, the VS pin also has these two functions: (4) senses the bulk capacitor input voltage to provide for ac-input run and stop thresholds, and (5) to compensate the current-sense threshold across the AC-input range. This information is sensed by monitoring the current pulled out of the VS pin during the MOSFET on-time. During this time the voltage on the VS pin is clamped to about 250 mV below GND. As a result, the current out of the pin is determined by the upper VS divider resistor, the auxiliary to primary turns-ratio and the bulk input voltage level. For the AC-input run/stop function, the run threshold on VS is IVSL(run) (typical 210 µA) and the stop threshold is IVSL(stop) (typical 75 µA). The values for the auxiliary voltage divider upper-resistor RS1 and lower-resistor RS2 can be determined by the equations below.

Equation 1. UCC28742 qu01_lusca8.gif

where

  • NPA is the transformer primary-to-auxiliary turns ratio,
  • VIN(run) is the AC rms voltage to enable turn-on of the flyback converter (run),
  • VBULK(run) is the DC bulk voltage to enable turn-on of the flyback converter (run),
  • IVSL(run) is the run-threshold for the current pulled out of the VS pin during the primary MOSFET on-time. (see the Electrical Characteristics table).
Equation 2. UCC28742 qu02_slusd71-equation1.gif

where

  • VOV is the maximum allowable peak voltage at the converter output,
  • VF is the output rectifier forward voltage drop at near-zero current,
  • NAS is the transformer auxiliary to secondary turns ratio,
  • RS1 is the VS divider upper-resistor resistance,
  • VOVP is the overvoltage detection threshold at the VS input (see the Electrical Characteristics table).

Notice that VS pin absolute maximum current IVS in its negative clamping is 1.2 mA. After determined RS1 it is required to check if VS pin current stays ≤ 1.2 mA. The check is to determine the input voltage ratio in this design and make VIN(max) / VIN(run) ≤ IVS / IVSL(run) = 1.2 mA / 0.25 mA = 4.8, i.e., VIN(max) / VIN(run) ≤ 4.8. If the design cannot meet this criterion, external circuit is needed to add in to make sure VS pin current ≤ 1.2 mA, for example, to use a zener type of device to clamp the transformer aux-winding negative voltage to achieve VIN(max) / VIN(run) ≤ 4.8.