JAJSF63 データシート

JAJSF63D April 2018 – September 2020 LMR36015

PRODUCTION DATA

8.5 Electrical Characteristics

Limits apply over operating junction temperature (T_J ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits⁽¹⁾ are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 24 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
I_Q-nonSW	Operating quiescent current (non-switching)⁽²⁾	V_EN = 3.3 V (PFM variant only)	18	26	36	µA
I_SD	Shutdown quiescent current; measured at VIN pin	V_EN= 0 V		5		µA
ENABLE (EN PIN)
V_EN-VCC-H	Enable input high level for V_CC output	V_ENABLE rising			1.14	V
V_EN-VCC-L	Enable input low level for V_CC output	V_ENABLE falling	0.3			V
V_EN-VOUT-H	Enable input high level for V_OUT	V_ENABLE rising	1.157	1.231	1.3	V
V_EN-VOUT-HYS	Enable input hysteresis for V_OUT	Hysteresis below V_ENABLE-H; falling		110		mV
I_LKG-EN	Enable input leakage current	V_EN = 3.3V		0.2		nA
INTERNAL LDO (VCC PIN)
V_CC	Internal V_CC voltage	6 V ≤ V_IN ≤ 60 V	4.75	5	5.25	V
V_{CC-UVLO-Rising}	Internal V_CC undervoltage lockout	V_CC rising	3.6	3.8	4.0	V
V_{CC-UVLO-Falling}	Internal V_CC undervoltage lockout	V_CC falling	3.1	3.3	3.5	V
VOLTAGE REFERENCE (FB PIN)
V_FB	Feedback voltage		0.985	1	1.015	V
I_LKG-FB	Feedback leakage current	FB = 1 V		0.2		nA
CURRENT LIMITS AND HICCUP
I_SC	High-side current limit⁽³⁾		2	2.4	2.8	A
I_LS-LIMIT	Low-side current limit⁽³⁾		1.55	1.8	2.07	A
I_L-ZC	Zero cross detector threshold	PFM variants only		0.02		A
I_PEAK-MIN	Minimum inductor peak current⁽³⁾			0.45		A
I_L-NEG	Negative current limit⁽³⁾	FPWM variant only	–1.8	–1.4	–0.9	A
POWER GOOD (PGOOD PIN)
V_PG-HIGH-UP	Power-Good upper threshold - rising	% of FB voltage	105%	107%	110%
V_PG-LOW-DN	Power-Good lower threshold - falling	% of FB voltage	90%	93%	95%
V_PG-HYS	Power-Good hysteresis (rising & falling)	% of FB voltage		2%
T_PG	Power-Good rising/falling edge deglitch delay		80	140	200	µs
V_PG-VALID	Minimum input voltage for proper Power-Good function				2	V
R_PG	Power-Good on-resistance	V_EN = 2.5 V		80	165	Ω
R_PG	Power-Good on-resistance	V_EN = 0 V		35	90	Ω
OSCILLATOR
F_OSC	Internal oscillator frequency	1-MHz variant	0.85	1	1.15	MHz
F_OSC	Internal oscillator frequency	400-kHz variant	340	400	460	kHz
MOSFETS
R_DS-ON-HS	High-side MOSFET ON-resistance	I_OUT= 0.5 A		225	435	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	I_OUT= 0.5 A		150	280	mΩ

(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.