JAJSF69A April   2018  – October 2018 ADS112C04

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      Kタイプ熱電対温度の測定
  4. 4 概要（続き）
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 I2C Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Stage
        1. 9.3.2.1 PGA Input Voltage Requirements
        2. 9.3.2.2 Bypassing the PGA
      3. 9.3.3  Voltage Reference
      4. 9.3.4  Modulator and Internal Oscillator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Conversion Times
      7. 9.3.7  Excitation Current Sources
      8. 9.3.8  Sensor Detection
      9. 9.3.9  System Monitor
      10. 9.3.10 Temperature Sensor
        1. 9.3.10.1 Converting From Temperature to Digital Codes
          1. 9.3.10.1.1 For Positive Temperatures (For Example, 50°C):
          2. 9.3.10.1.2 For Negative Temperatures (For Example, –25°C):
        2. 9.3.10.2 Converting From Digital Codes to Temperature
      11. 9.3.11 Offset Calibration
      12. 9.3.12 Conversion Data Counter
      13. 9.3.13 Data Integrity Features
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up and Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Conversion Modes
        1. 9.4.2.1 Single-Shot Conversion Mode
        2. 9.4.2.2 Continuous Conversion Mode
      3. 9.4.3 Operating Modes
        1. 9.4.3.1 Normal Mode
        2. 9.4.3.2 Turbo Mode
        3. 9.4.3.3 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
        1. 9.5.1.1 I2C Address
        2. 9.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
        3. 9.5.1.3 Data Ready (DRDY)
        4. 9.5.1.4 Interface Speed
        5. 9.5.1.5 Data Transfer Protocol
        6. 9.5.1.6 I2C General Call (Software Reset)
        7. 9.5.1.7 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1 Command Latching
        2. 9.5.3.2 RESET (0000 011x)
        3. 9.5.3.3 START/SYNC (0000 100x)
        4. 9.5.3.4 POWERDOWN (0000 001x)
        5. 9.5.3.5 RDATA (0001 xxxx)
        6. 9.5.3.6 RREG (0010 rrxx)
        7. 9.5.3.7 WREG (0100 rrxx dddd dddd)
      4. 9.5.4 Reading Data and Monitoring for New Conversion Results
      5. 9.5.5 Data Integrity
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1 Configuration Register 0 (address = 00h) [reset = 00h]
          1. Table 19. Configuration Register 0 Field Descriptions
        2. 9.6.2.2 Configuration Register 1 (address = 01h) [reset = 00h]
          1. Table 20. Configuration Register 1 Field Descriptions
        3. 9.6.2.3 Configuration Register 2 (address = 02h) [reset = 00h]
          1. Table 22. Configuration Register 2 Field Descriptions
        4. 9.6.2.4 Configuration Register 3 (address = 03h) [reset = 00h]
          1. Table 23. Configuration Register 3 Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interface Connections
      2. 10.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 10.1.3 Unused Inputs and Outputs
      4. 10.1.4 Analog Input Filtering
      5. 10.1.5 External Reference and Ratiometric Measurements
      6. 10.1.6 Establishing Proper Limits on the Absolute Input Voltage
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Applications
      1. 10.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Resistive Bridge Measurement
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

10.2.2.2 Detailed Design Procedure

The circuit in Figure 74 employs a ratiometric measurement approach. In other words, the sensor signal (that is, the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out because these errors are common to both the sensor signal and the reference.

In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision, low-drift reference resistor, RREF. The voltage, VREF, generated across the reference resistor (as shown in Equation 11) is used as the ADC reference voltage. Equation 11 reduces to Equation 12 because IIDAC1 = IIDAC2.

Equation 11. VREF = (IIDAC1 + IIDAC2) · RREF
Equation 12. VREF = 2 · IIDAC1 · RREF

To simplify the following discussion, the individual lead resistance values of the RTD (RLEADx) are set to zero. As Equation 13 shows, only IDAC1 excites the RTD to produce a voltage (VRTD) proportional to the temperature-dependent RTD value and the IDAC1 value.

Equation 13. VRTD = RRTD (at temperature) · IIDAC1

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code proportional to Equation 14 through Equation 16:

Equation 14. Code ∝ VRTD · Gain / VREF
Equation 15. Code ∝ (RRTD (at temperature) · IIDAC1 · Gain) / (2 · IIDAC1 · RREF)
Equation 16. Code ∝ (RRTD (at temperature) · Gain) / (2 · RREF)

As shown in Equation 16, the output code only depends on the value of the RTD, the PGA gain, and the reference resistor (RREF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly affects the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of RREF.

The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance. Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, use Equation 17 to calculate the differential voltage (VIN) across the ADC inputs (AIN0 and AIN1):

Equation 17. VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2

Equation 17 reduces to Equation 18 when RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2:

Equation 18. VIN = IIDAC1 · RRTD

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are well matched.

A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC inputs, as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The same guidelines for designing the input filter apply as described in the K-Type Thermocouple Measurement section. Match the corner frequencies of the input and reference filter for best performance. For more detailed information on matching the input and reference filter, see the RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 application report.

The reference resistor RREF not only serves to generate the reference voltage for the device, but also sets the voltages at the leads of the RTD to within the specified absolute input voltage range of the PGA.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs. The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal to or less than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 19 must be met at all times.

Equation 19. AVSS + IIDAC1 · (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) · (RLEAD3 + RREF) ≤ AVDD – 0.9 V

The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter resistor values RF1 and RF2 in Figure 74 are small enough and well matched, then IDAC1 can be routed to AIN1 and IDAC2 to AIN0. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with a single device.

As stated in Table 26, this design example discusses the implementation of a 3-wire Pt100 measurement to be used to measure temperatures ranging from –200°C to +850°C. The excitation current for the Pt100 is chosen as IIDAC1 = 500 µA, which means a combined current of 1 mA is flowing through the reference resistor, RREF. As mentioned previously, besides creating the reference voltage for the ADS112C04, the voltage across RREF also sets the absolute input voltages for the RTD measurement. In general, choose the largest reference voltage possible that maintains the compliance voltage of the IDACs and meets the absolute input voltage requirement of the PGA. Setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V) in most cases satisfies the absolute input voltage requirements of the PGA. Equation 20 is then used to calculate the value for RREF:

Equation 20. RREF = VREF / (IIDAC1 + IIDAC2) = 1.65 V / 1 mA = 1.65 kΩ

The stability of RREF is critical to achieve good measurement accuracy over temperature and time. Choosing a reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65-kΩ value is not readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.

As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured (VINMAX) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 21:

Equation 21. VINMAX = VRTD (at 850°C) = RRTD (at 850°C) · IIDAC1 = 391 Ω · 500 µA = 195.5 mV

The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV) = 8.4. The next smaller PGA gain setting available in the ADS112C04 is 8. At a gain of 8, the ADS112C04 offers a FSR value as described in Equation 22:

Equation 22. FSR = ±VREF / Gain = ±1.65 V / 8 = ±206.25 mV

This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.

After selecting the values for the IDACs, RREF, and PGA gain, make sure to double check that the settings meet the absolute input voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the true absolute input voltages at the ADC inputs (AIN0 and AIN1), the lead resistance must be taken into account as well.

The smallest absolute input voltage occurs on AIN0 at the lowest measurement temperature (–200°C) with RLEADx = 0 Ω, and is equal to VREF = 1.65 V.

The minimum absolute input voltage must not exceed the limit set in Equation 7 to meet Equation 23:

Equation 23. VAIN0 (MIN) ≥ AVSS + 0.2 V + |VINMAX| · (Gain – 4) / 8 = 0 V + 0.2 V + 97.75 mV = 297.75 mV

The restriction is satisfied with VAIN0 = 1.65 V.

The largest absolute input voltage (calculated using Equation 24 and Equation 25) occurs on AIN1 at the highest measurement temperature (850°C).

Equation 24. VAIN1 (MAX) = VREF + (IIDAC1 + IIDAC2) · RLEAD3 + IIDAC1 · (RLEAD1 + RRTD (at 850°C))
Equation 25. VAIN1 (MAX) = 1.65 V + 1 mA · 15 Ω + 500 µA · (15 Ω + 391 Ω) = 1.868 V

VAIN1 (MAX) meets the requirement given by Equation 7 and equates to Equation 26 in this design:

Equation 26. VAINP (MAX) ≤ AVDD – 0.2 V – |VINMAX| · (Gain – 4) / 8 = 3.3 V – 0.2 V – 97.75 mV = 3.002 V

The restriction on the compliance voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met as well.

Table 27 shows the register settings for this design.

Table 27. Register Settings

REGISTER SETTING DESCRIPTION
00h 36h AINP = AIN1, AINN = AIN0, gain = 8, PGA enabled
01h 0Ah DR = 20 SPS, normal mode, continuous conversion mode, external reference
02h 55h Conversion data counter disabled, data integrity disabled, burnout current sources disabled, IDAC = 500 µA
03h 70h IDAC1 = AIN2, IDAC2 = AIN3