JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The OUTCTL_5 register provides control over Output 5.
Bit # | Field | Type | Reset | EEPROM | Description | ||
---|---|---|---|---|---|---|---|
[7:6] | CH_5_MUX[1:0] | RW | 0x0 | Y | Channel 5 Clock Source Mux Control. | ||
CH_5_MUX | CH5 Clock Source | ||||||
0 (0x0) | PLL | ||||||
1 (0x1) | Reserved | ||||||
2 (0x2) | PRIMARY REFERENCE | ||||||
3 (0x3) | SECONDARY REFERENCE | ||||||
When the doubler is enabled the Primary and Secondary Reference options will reflect the frequency doubled reference. If the Primary or Secondary Reference options are selected the output divider is by-passed. | |||||||
[5:4] | OUT_5_SEL[1:0] | RW | 0x1 | Y | Channel 5 Output Driver Format Select. The OUT_5_SEL field controls the Channel 5 Output Driver as shown below. | ||
OUT_1_SEL | OUTPUT OPERATION | ||||||
0 (0x0) | Disabled | ||||||
1 (0x1) | AC-LVDS/AC-CML/AC-LVPECL | ||||||
2 (0x2) | HCSL | ||||||
3 (0x3) | LVCMOS | ||||||
[3:2] | OUT_5_MODE1[1:0] | RW | 0x2 | Y | Channel 5 Output Driver Mode1 Select. | ||
OUT_5_MODE1 | Diff-Mode, Itail | CMOS-Mode, Out_P | |||||
0 (0x0) | 4 mA (AC-LVDS) | Powerdown, tristate | |||||
1 (0x1) | 6 mA (AC-CML) | Powerdown, low | |||||
2 (0x2) | 8 mA (AC-LVPECL) | Powerup, negative polarity | |||||
3 (0x3) | 16 mA (HCSL) or 8 mA (AC-LVPECL) | Powerup, positive polarity | |||||
[1:0] | OUT_5_MODE2[1:0] | RW | 0x0 | Y | Channel 5 Output Driver Mode2 Select. | ||
OUT_5_MODE2 | Diff-Mode, Rload in HCSL mode | CMOS=Mode, Out_N | |||||
0 (0x0) | Tristate | Powerdown, tristate | |||||
1 (0x1) | 50 Ω | Powerdown, low | |||||
2 (0x2) | 100 Ω | Powerup, negative polarity | |||||
3 (0x3) | 200 Ω | Powerup, positive polarity |