JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
Channel 5 Output Divider
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:0] | OUT_5_DIV[7:0] | RW | 0x02 | Y | Channel 5 Output Divider. The Channel 5 Divider, OUT_5_DIV, is a 8-bit divider. The valid values for OUT_5_DIV range from 1 to 256 as shown below. The divider only operates on Channel 5 when the clock source is PLL or PLL2. | |
OUT_5_DIV | DIVIDE RATIO | |||||
0 (0x00) | 1 | |||||
1 (0x01) | 2 | |||||
2 (0x02) | 3 | |||||
... | ||||||
255 (0xFF) | 256 |