JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The PLL_CTRL0 register provides control of PLL. The PLL_CTRL0 register fields are described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:5] | RSRVD | - | - | N | Reserved. | |
[4:2] | PLL_P[2:0] | RW | 0x7 | Y | PLL Post-Divider. The PLL_P field selects the PLL post-divider value as follows. | |
PLL_P | Post Divider Value | |||||
0 (0x0) | 2 | |||||
1 (0x1) | 2 | |||||
2 (0x2) | 3 | |||||
3 (0x3) | 4 | |||||
4 (0x4) | 5 | |||||
5 (0x5) | 6 | |||||
6 (0x6) | 7 | |||||
7 (0x7) | 8 | |||||
[1] | PLL_SYNC_EN | RW | 1 | Y | PLL SYNC Enable. If PLL_SYNC_EN is 1 then a SYNC event will cause all channels which use PLL as a clock source to be re-synchronized. | |
[0] | PLL_PDN | RW | 0 | Y | PLL Powerdown. The PLL_PDN bit determines whether PLL is automatically enabled and calibrated after a hardware reset. If the PLL_PDN bit is set to 1 during normal operation then PLL is disabled and the calibration circuit is reset. When PLL_PDN is then cleared to 0 PLL is re-enabled and the calibration sequence is automatically restarted. | |
PLL_PDN | PLL STATE | |||||
0 | PLL Enabled | |||||
1 | PLL Disabled |