11.2.4.1 Detailed Design Procedure

Design of all aspects of the LMK03318 is quite involved, and software support is available to assist in part selection, part programming, loop filter design, and phase-noise simulation. This design procedure will give a quick outline of the process.

1. Device Selection
   • The first step to calculate the specified VCO frequency given required output frequencies. The device must be able to produce the VCO frequency that can be divided down to the required output frequencies.
   • The WEBENCH Clock Architect Tool from TI will aid in the selection of the right device that meets the customer's output frequencies and format requirements.
2. Device Configuration
   • There are many device configurations to achieve the desired output frequencies from a device. However there are some optimizations and trade-offs to be considered.
   • The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
   • These guidelines below may be followed when configuring PLL related dividers or other related registers:
     • For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
     • For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
     • To reduce loop filter component sizes, increase N value and/or reduce charge pump current.
     • For fractional divider values, keep the denominator at highest value possible to minimize spurs. It is also best to use higher order modulator wherever possible for the same reason.
     • As a rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 * PLL bandwidth may be unstable and a phase detector frequency > 100 * loop bandwidth may experience increased lock time due to cycle slipping.
3. PLL Loop Filter Design
   • TI recommends using the WEBENCH Clock Architect Tool to design your loop filter.
   • Optimal loop filter design and simulation can be achieved when custom reference phase noise profiles are loaded into the software tool.
   • While designing the loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but may increase impacts of leakage and reduce PLL phase noise performance.
   • For a more detailed understanding of loop filter design can be found in Dean Banerjee's PLL Performance, Simulation, and Design (www.ti.com/tool/pll_book).
4. Clock Output Assignment
   • At the time of writing this datasheet, the design software does not take into account frequency assignment to specific outputs except to ensure that the output frequencies can be achieved. It is best to consider proximity of the clock outputs to each other and other PLL circuitry when choosing final clock output locations. Here are some guidelines to help achieve optimal performance when assigning outputs to specific clock output pins.
     • Group common frequencies together.
     • PLL charge pump circuitry can cause crosstalk at the charge pump frequency. Place outputs sharing charge pump frequency or lower priority outputs not sensitive to charge pump frequency spurs together.
     • Clock output MUXes can create a path for noise coupling. Factor in frequencies which may have some bleedthrough from non-selected mux inputs.
     • If possible, use outputs 0, 1, 2 or 3 since they don’t have MUX in the clock path and have limited opportunity for cross coupled noise.
5. Device Programming
   • The EVM programming software tool CodeLoader can be used to program the device with the desired configuration.