JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The PLL’s loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip. The PLL unlock is detected when a certain number of cycle slips have been exceeded, at which point the counter is reset. If the loss of lock is intended to toggle a system reset, an RC filter on the status output, which is programmed to indicate loss of lock, is recommended to avoid rare cycle slips from triggering an entire system reset.
| NUMBER | SIGNAL |
|---|---|
| 0 | PRIREF Loss of Signal (LOS) |
| 1 | SECREF Loss of Signal (LOS) |
| 2 | PLL Loss of Lock (LOL) |
| 3 | PLL R Divider, divided by 2 (when R Divider is not bypassed) |
| 4 | PLL N Divider, divided by 2 |
| 5 | RESERVED |
| 6 | RESERVED |
| 7 | RESERVED |
| 8 | PLL VCO Calibration Active (CAL) |
| 9 | RESERVED |
| 10 | Interrupt (INTR) |
| 11 | PLL M Divider, divided by 2 (when M Divider is not bypassed) |
| 12 | RESERVED |
| 13 | EEPROM Active |
| 14 | PLL Secondary to Primary Switch in Automatic Mode |
| 15 | RESERVED |
When the status pins are programmed as 3.3-V LVCMOS PLL clock outputs with fast output rise/fall time setting, they support up to 200 MHz operation and each output can independently be programmed to different frequencies. Each output has the option to be muted or not, in case the PLL from which it is derived loses lock, by programming R23 and when muted, the output is held at a static state depending on the programmed output type/polarity. in a loss-of-lock event. To reduce coupling onto the high-speed outputs, the output rise/fall time can be modified in R49 to support slower slew rates.
NOTE
When either status pin is set as a 3.3-V LVCMOS output, there is fairly significant mixing of these output frequencies into the high-speed outputs, especially outputs 4, 5, 6, and 7. If 3.3-V LVCMOS outputs are desired, proper care should be taken during frequency planning with the LMK03318 to ensure that the outputs, required with low jitter, are selected from either output 0, 1, 2, or 3. For best jitter performance, TI recommends using both status pins to generate complementary 3.3-V LVCMOS outputs at any time.