JAJSFF4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
      1.      改訂履歴
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 はじめに
    2. 7.2 デバイスの項目表記
    3. 7.3 ツールとソフトウェア
    4. 7.4 ドキュメントのサポート
    5. 7.5 関連リンク
    6. 7.6 商標
    7. 7.7 静電気放電に関する注意事項
    8. 7.8 Glossary
  8. 8メカニカル、パッケージ、および注文情報

5.10.7 Interrupt Compare Controller (ICC)

The Interrupt Compare Controller (ICC) allows all maskable interrupt sources to be scheduled in a preemptive mechanism. Each interrupt source is specified as a source of ICC module. Each source supports a 4-level software interrupt priority other than the one tired with interrupt vector. When ICC module is enabled, the ISR in lower software priority can be interrupted by higher priority. It is required to enable GIE in ISR for proper ICC operation. For details, see the ICC chapter of the MSP430FR4xx and MSP430FR2xx Family User's Guide. Table 5-13 lists the ICC source configurations.

Table 5-13 ICC Interrupt Source Assignments

REGISTER BITS INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
ICCILRS0 ILSR0 P4 P4IFG.0 to P4IFG.7 (P4IV) Maskable FFCEh 39
ILSR1 P3 P3IFG.0 to P3IFG.7 (P3IV) Maskable FFD0h 40
ILSR2 P2 P2IFG.0 to P2IFG.7 (P2IV) Maskable FFD2h 41
ILSR3 P1 P1IFG.0 to P1IFG.7 (P1IV) Maskable FFD4h 42
ILSR4 SAC3 DAC, SAC1 DAC(1) DACIFG, (SAC3IV, SAC1IV)(1) Maskable FFD6h 43
ILSR5 SAC2 DAC, SAC0 DAC(1) DACIFG (SAC2IV, SAC0IV)(1) Maskable FFD8h 44
ILSR6 eCOMP1, eCOMP0 CPIIFG, CPIFG (CP1IV, CP0IV) Maskable FFDAh 45
ILSR7 ADC ADCIFG0, ADCINIFG, ADCLOIFG, ADCHIIFG, ADCTOVIFG, ADCOVIFG (ADCIV) Maskable FFDCh 46
ICCILRS1 ILSR8 eUSCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)		 Maskable FFDEh 47
ILSR9 eUSCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG,UCCLTOIFG(I2C mode)
(UCB0IV)		 Maskable FFE0h 48
ILSR10 eUSCI_A1 Receive or Transmit UCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))		 Maskable FFE2h 49
ILSR11 eUSCI_A0 Receive or Transmit UCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))		 Maskable FFE4h 50
ILSR12 Watchdog Timer Interval mode WDTIFG Maskable FFE6h 51
ILSR13 RTC Counter RTCIFG Maskable FFE8h 52
ILSR14 Timer3_B7 TB3CCR1 CCIFG1, TB3CCR2 CCIFG2, TB3CCR3 CCIFG3, TB3CCR4 CCIFG4, TB3CCR5 CCIFG5, TB3CCR6 CCIFG6, TB3IFG (TB3IV) Maskable FFEAh 53
ILSR15 Timer3_B7 TB3CCR0 CCIFG0 Maskable FFECh 54
ICCILRS2 ILSR16 Timer2_B3 TB2CCR1 CCIFG1, TB2CCR2 CCIFG2, TB2IFG (TB2IV) Maskable FFEEh 55
ILSR17 Timer2_B3 TB2CCR0 CCIFG0 Maskable FFF0h 56
ILSR18 Timer1_B3 TB1CCR1 CCIFG1, TB1CCR2 CCIFG2, TB1IFG (TB1IV) Maskable FFF2h 57
ILSR19 Timer1_B3 TB1CCR0 CCIFG0 Maskable FFF4h 58
ILSR20 Timer0_B3 TB0CCR1 CCIFG1, TB0CCR2 CCIFG2, TB0IFG (TB0IV) Maskable FFF6h 59
ILSR21 Timer0_B3 TB0CCR0 CCIFG0 Maskable FFF8h 60
ILSR22 N/A N/A N/A N/A N/A
ILSR23 N/A N/A N/A N/A N/A
ICCILRS3 ILSR24 N/A N/A N/A N/A N/A
ILSR25 N/A N/A N/A N/A N/A
ILSR26 N/A N/A N/A N/A N/A
ILSR27 N/A N/A N/A N/A N/A
ILSR28 N/A N/A N/A N/A N/A
ILSR29 N/A N/A N/A N/A N/A
ILSR30 N/A N/A N/A N/A N/A
ILSR31 N/A N/A N/A N/A N/A
(1) MSP430FR235x devices only