JAJSFF5F September   2007  – October 2018 DAC5652A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     機能ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC
    6. 6.6  Electrical Characteristics: AC
    7. 6.7  Electrical Characteristics: Digital Input
    8. 6.8  Electrical Characteristics: Power Supply
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Inputs
      2. 7.3.2 References
        1. 7.3.2.1 Internal Reference
        2. 7.3.2.2 External Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Interfaces
        1. 7.4.1.1 Dual-Bus Data Interface and Timing
        2. 7.4.1.2 Single-Bus Interleaved Data Interface and Timing
      2. 7.4.2 Gain Setting Option
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DAC Transfer Function
        1. 8.1.1.1 Analog Outputs
      2. 8.1.2 Output Configurations
      3. 8.1.3 Differential With Transformer
      4. 8.1.4 Single-Ended Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics: DC

dc specifications over TA, AVDD = DVDD = 3.3 V, I(OUTFS) = 20 mA, and independent gain set mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 10 Bits
DC ACCURACY(1)
INL Integral nonlinearity 1 LSB = I(OUTFS)/210, TMIN to TMAX –1 ±0.25 1 LSB
DNL Differential nonlinearity –0.5 ±0.16 0.5 LSB
ANALOG OUTPUT
Offset error Midscale value (internal reference) ±0.05 %FSR
Offset mismatch Midscale value (internal reference) ±0.03 %FSR
Gain error With internal reference ±0.75 %FSR
Minimum full-scale output current(2) 2 mA
Maximum full-scale output current(2) 20 mA
Gain mismatch With internal reference –2 0.2 2 %FSR
Output voltage compliance range(1) –1 1.25 V
RO Output resistance 300 kΩ
CO Output capacitance 5 pF
REFERENCE OUTPUT
Reference voltage 1.14 1.2 1.26 V
Reference output current(3) 100 nA
REFERENCE INPUT
V(EXTIO) Input voltage 0.1 1.25 V
RI Input resistance 1 MΩ
Small signal bandwidth 300 kHz
CI Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
Offset drift 2 ppm of FSR/°C
Gain drift With external reference ±20 ppm of FSR/°C
With internal reference ±40
Reference voltage drift ±20 ppm/°C
(1) Measured differentially through 50 Ω to AGND.
(2) Nominal full-scale current, I(OUTFS), equals 32x the I(BIAS) current.
(3) Use an external buffer amplifier with high-impedance input to drive any external load.