JAJSFF5F September   2007  – October 2018 DAC5652A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     機能ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC
    6. 6.6  Electrical Characteristics: AC
    7. 6.7  Electrical Characteristics: Digital Input
    8. 6.8  Electrical Characteristics: Power Supply
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Inputs
      2. 7.3.2 References
        1. 7.3.2.1 Internal Reference
        2. 7.3.2.2 External Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Interfaces
        1. 7.4.1.1 Dual-Bus Data Interface and Timing
        2. 7.4.1.2 Single-Bus Interleaved Data Interface and Timing
      2. 7.4.2 Gain Setting Option
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DAC Transfer Function
        1. 8.1.1.1 Analog Outputs
      2. 8.1.2 Output Configurations
      3. 8.1.3 Differential With Transformer
      4. 8.1.4 Single-Ended Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

PFB Package
48-Pin TQFP
Top View
RSL Package
48-Pin VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME TQFP VQFN
AGND 38 26 I Analog ground
AVDD 47 35 I Analog supply voltage
BIASJ_A 44 32 O Full-scale output current bias for DACA
BIASJ_B 41 29 O Full-scale output current bias for DACB
CLKA/CLKIQ 18 6 I Clock input for DACA, CLKIQ in interleaved mode
CLKB/RESETIQ 19 7 I Clock input for DACB, RESETIQ in interleaved mode
DA0 10 46 I Data port A0 (LSB). Internal pulldown.
DA1 9 45 I Data port A1. Internal pulldown.
DA2 8 44 I Data port A2. Internal pulldown.
DA3 7 43 I Data port A3. Internal pulldown.
DA4 6 42 I Data port A4. Internal pulldown.
DA5 5 41 I Data port A5. Internal pulldown.
DA6 4 40 I Data port A6. Internal pulldown.
DA7 3 39 I Data port A7. Internal pulldown.
DA8 2 38 I Data port A8. Internal pulldown.
DA9 1 37 i Data port A9 (MSB). Internal pulldown.
DB0 32 20 I Data port B0 (LSB). Internal pulldown.
DB1 31 19 I Data port B1. Internal pulldown.
DB2 30 18 I Data port B2. Internal pulldown.
DB3 29 17 I Data port B3. Internal pulldown.
DB4 28 16 I Data port B4. Internal pulldown.
DB5 27 15 I Data port B5. Internal pulldown.
DB6 26 14 I Data port B6. Internal pulldown.
DB7 25 13 I Data port B7. Internal pulldown.
DB8 24 12 I Data port B8. Internal pulldown.
DB9 23 11 I Data port B9 (MSB). Internal pulldown.
DGND 15, 21 3, 9 I Digital ground
DVDD 16, 22 4, 10 I Digital supply voltage
EXTIO 43 31 I/O Internal reference output (bypass with 0.1 μF to AGND) or external reference input
GSET 42 30 I Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup.
IOUTA1 46 34 O DACA current output. Full-scale with all bits of DA high.
IOUTA2 45 33 O DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1 39 27 O DACB current output. Full-scale with all bits of DB high.
IOUTB2 40 28 O DACB complementary current output. Full-scale with all bits of DB low.
MODE 48 36 I Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
NC 11-14, 33-36 1,2, 21-24, 47, 48 — Factory use only. Pins must be connected to DGND or left unconnected.
SLEEP 37 25 I Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal pulldown.
WRTA/WRTIQ 17 5 I Input write signal for PORT A (WRTIQ in interleaving mode)
WRTB/SELECTIQ 20 8 I Input write signal for PORT B (SELECTIQ in interleaving mode)