JAJSFF8E October 2012 – May 2018 BQ27545-G1
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
SRP | A1 | IA | Analog input pin connected to the internal coulomb counter where SRP is nearest the CELL– connection. Connect to a 5-mΩ to 20-mΩ sense resistor. |
SRN | B1 | IA | Analog input pin connected to the internal coulomb counter where SRN is nearest the PACK– connection. Connect to the 5-mΩ to 20-mΩ sense resistor. |
VSS | C1, C2 | P | Device ground |
SE | C3 | O | Shutdown Enable output. Push-pull output. |
VCC | D1 | P | Regulator output and processor power. Decouple with 1-µF ceramic capacitor to VSS. |
REGIN | E1 | P | Regulator input. Decouple with 0.1-µF ceramic capacitor to VSS. |
HDQ | A2 | I/O | HDQ serial communications line (Slave). Open drain. |
TS | B2 | IA | Pack thermistor voltage sense (use 103AT-type thermistor). ADC input. |
CE | D2 | I | Chip Enable. Internal LDO is disconnected from REGIN when driven low. |
BAT | E2 | IA | Cell-voltage measurement input. ADC input. Recommend 4.8-V maximum for conversion accuracy. |
SCL | A3 | I | Slave I2C serial communications clock input line for communication with system (Master). Use with 10-kΩ pullup resistor (typical). |
SDA | B3 | I/O | Slave I2C serial communications data line for communication with system (Master). Open-drain I/O. Use with 10-kΩ pullup resistor (typical). |
NC/GPIO | D3, E3 | NC | Do not connect for proper operation; reserved for future GPIO. |