JAJSFF8E October 2012 – May 2018 BQ27545-G1
PRODUCTION DATA.
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to the bq27545-G1. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first. The DATA signal on pin 12 is open drain and requires an external pullup resistor. The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB bit 7). The R/W field directs the bq27545-G1 either to
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
HDQ serial communication is normally initiated by the host processor sending a break command to the bq27545-G1. A break is detected when the DATA pin is driven to a logic-low state for a time t(B) or greater. The DATA pin should then be returned to its normal ready high logic state for a time t(BR). The bq27545-G1 is now ready to receive information from the host processor.
The bq27545-G1 is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral. The HDQ Communication Basics Application Report (SLUA408A) provides details of HDQ communication basics.