7.3.10 Internal LDO and BIAS_SEL

The LMZM33606 integrates an internal LDO, generating a typical V_CC voltage (3.27 V) for control circuitry and MOSFET drivers. The LDO generates V_CC voltage from V_IN unless a sufficient bias voltage, V_BIAS, is applied to BIAS_SEL pin. The BIAS_SEL input provides an option to supply the LDO with a lower voltage than V_IN to reduce the LDO power loss. The smaller the difference between the input applied to the LDO, V_{IN_LDO}, and the LDO output voltage, V_CC, the more efficiently the device will perform. The amount of current supplied through the LDO will change based on operating conditions. Figure 36 demonstrates the typical LDO current, I_LDO, for common input voltages over the recommended switching frequency range.

The amount of power loss in the LDO can be calculated by Equation 4.

For example, when the device is operating at V_IN = 24 V, V_OUT = 5 V, f_sw = 500 kHz, BIAS_SEL = PGND, the I_LDO is typical 11 mA, therefore, the P_{LOSS_LDO} = 11 mA × (24 V – 3.27 V) = 228.03 mW. For the same operating conditions with BIAS_SEL = 5 V, the power loss is equal to 11 mA × (5 V – 3.27 V) = 19.03 mW. The benefits of applying a bias voltage to reduce power loss are most notable in applications when V_IN » V_CC or when the device is operating at a higher switching frequency. The power savings can be calculated by Equation 5.

Figure 37 and Figure 38 show efficiency plots of the LMZM33606 operating with different source voltages applied to the BIAS_SEL pin. Figure 39 demonstrates the power dissipation of the device with various source voltages at BIAS_SEL pin. The plots include BIAS_SEL tied to a 3.3 V external bias, 5 V external bias, VOUT (5 V) and no bias voltage applied. The efficiency improvements are more significant when the device is operating at light loads because the LDO loss is a higher percentage of the total loss.