JAJSFO0G september   2012  – october 2020 SN65DSI85

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-24B27461-2407-4A70-B6CA-5D1E4961612D/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8.   Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 24
      3. 7.4.3 Reset Implementation
      4. 7.4.4 Initialization Sequence
      5. 7.4.5 LVDS Output Formats
      6. 7.4.6 DSI Lane Merging
      7. 7.4.7 DSI Pixel Stream Packets
      8. 7.4.8 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Typical WUXGA 18-bpp Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Script
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Typical WQXGA 24-bpp Application
        1. 8.2.2.1 Design Requirements
  11. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  12. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from Revision F (June 2018) to Revision G (October 2020)

  • u*jr ZQE を nFBGA ZXH に変更Go
  • Changed u*jr ZQE to nFBGA ZXHGo
  • Changed u*jr ZQE to nFBGA ZXH. Updated thermal information.Go
  • Changed u*jr ZQE to nFBGA ZXHGo

Changes from Revision E (August 2015) to Revision F (June 2018)

  • Deleted figure RESET and Initialization Timing Definition While VCC is High Go
  • Changed the paragraph following Figure 7-3 Go
  • Changed Recommended Initialization Sequence To: Initialization Sequence Go
  • Changed Table 7-5 Go
  • Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. Go

Changes from Revision D (September 2013) to Revision E (August 2015)

  • 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 Go
  • Changed item 3 of the ULPS sequence list for clarification. Go
  • Changed description of the Init seq 7 - Recommended Initialization Sequence for clarification. Go
  • Changed description of Address 0x0A, Bit 7 in Table 7-8, CSR Bit Field Definitions - Reset and Clock Registers Go
  • Changed Address 0x18, Bits 3 and 2 Description, Address 0x18, Bit 1 Description, and Address 0x18, Bit 0 Description in Table 7-10 for clarification.Go
  • Changed Address 0x18, Bit 1 Description in Table 7-10 for clarification. Go
  • Changed Address 0x18, Bit 0 Description in Table 7-10 for clarification.Go
  • Changed Section 8.1.1, step 1 of the STOP sequence from " ...0(CSR 0x0A.7)" to "....0(CSR 0x0D.0)” and step 3 of the Restart sequence from "Wait for the PLL_LOCK bit to be set(CSR 0x0A.7)." to "Wait for a minimum of 3 ms." Go
  • Changed Section 8.1.1, step 3 of the Restart sequence from "Wait for the PLL_LOCK bit to be set(CSR 0x0A.7)." to "Wait for a minimum of 3 ms."Go

Changes from Revision * (August 2012) to Revision A (December 2012)

  • Changed the tsetup and thold NOM value of 1.5 to a MIN value of 1.5Go
  • Changed the value of VOH From: 1.3 MIN To: 1.25 MINGo
  • Changed the ICC TYP value From: 125 To: 127 and MAX value From: 200 To: 212 Go
  • Added a TYP value of 7.7 to IULPS Go
  • Changed the IRST TYP value From: 0.05 To: 0.04 and MAX value From: 0.2 To: 0.06Go
  • changed the values of |VOD|Go
  • changed the values of |VOD|Go
  • Changed the values of VOC(SS) for test conditions CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0Go
  • Added table note 2Go
  • Added table note 3Go
  • Changed the SWITCHING CHARACTERISTICS tableGo
  • Changed the description of CHA_LVDS_VOD_SWINGGo
  • Changed the description of CHB_LVDS_VOD_SWINGGo