JAJSFO2I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

LVDS Output Formats

The SN65DSI83 device processes DSI packets and produces video data driven to the FlatLink LVDS interface in an industry standard format. Single-Link LVDS is supported by the SN65DSI83 device. During conditions such as the default condition, and some video synchronization periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI83 device transmits zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync status.

Figure 7-4 illustrates a Single-Link LVDS 18 bpp application.

Figure 7-5 illustrates a Single-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane.

Figure 7-6 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are transferred on the Y3P/N LVDS lane.

Figure 7-7 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to
18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to 1 and CHA_24BPP_MODE (CSR 0x18.3) to 0. In this configuration, the SN65DSI83 device does not transmit the 2 LSB per color since the Y3P and Y3N LVDS lane is disabled.

Note:

Figure 7-4, Figure 7-5, Figure 7-6, and Figure 7-7 only illustrate a few example applications for the SN65DSI83 device. Other applications are also supported.

GUID-C49A556E-4F69-4A85-A5C8-52497860B80D-low.gif
DE = Data Enable; A_Y3P/N are Output Low
Figure 7-4 FlatLink Output Data; Single-Link 18 bpp
GUID-7B01A4A4-0D62-4649-BD94-6DD823EC5149-low.gif
DE = Data Enable
Figure 7-5 FlatLink Output Data (Format 2); Single-Link 24 bpp
GUID-85632311-0AAC-41EE-A496-4A989656B854-low.gif
DE = Data Enable
Figure 7-6 FlatLink Output Data (Format 1); Single-Link 24 bpp
GUID-761B2E83-F60D-4C55-9AC3-18EB676109A9-low.gif
DE = Data Enable; A_Y3P and A_Y3N are output low; A_Y3P and A_Y3N are output low
Figure 7-7 FlatLink Output Data (Format 1); 24 bpp to Single-Link 18 bpp Conversion