JAJSFU0A July   2018  – October 2021 TPS3430

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 Window Watchdog
        1. 7.3.2.1 SET0 and SET1
          1. 7.3.2.1.1 Enabling the Window Watchdog
          2. 7.3.2.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.2.1.3 SET0 and SET1 During Normal Watchdog Operation
      3. 7.3.3 Window Watchdog Timer
        1. 7.3.3.1 CWD
        2. 7.3.3.2 WDI Functionality
        3. 7.3.3.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 VDD is Above VPOR And Below VDD (min)( VPOR < VDD < VDD (min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Watchdog Reset Delay Timing
        2. 8.1.1.2 CRST Programmable Watchdog Reset Delay
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 CWD Adjustable Capacitor Watchdog Timeout
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Microcontroller with Watchdog Timer - Design 1
        1. 8.2.1.1 Design Requirements - Design 1
        2. 8.2.1.2 Detailed Design Procedure - Design 1
          1. 8.2.1.2.1 Meeting the Minimum Watchdog Reset Delay - Design 1
          2. 8.2.1.2.2 Setting the Watchdog Window - Design 1
          3. 8.2.1.2.3 Calculating the WDO Pull-up Resistor - Design 1
      2. 8.2.2 Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2
        1. 8.2.2.1 Design Requirements - Design 2
        2. 8.2.2.2 Detailed Design Procedure - Design 2
          1. 8.2.2.2.1 Meeting the Minimum Watchdog Reset Delay - Design 2
          2. 8.2.2.2.2 Setting the Watchdog Window - Design 2
          3. 8.2.2.2.3 Calculating the WDO Pull-up Resistor - Design 2
      3. 8.2.3 Monitoring Microcontroller with a Latching Window Watchdog Timer - Design 3
        1. 8.2.3.1 Design Requirements - Design 3
        2. 8.2.3.2 Detailed Design Procedure - Design 3
          1. 8.2.3.2.1 Meeting the Latching Output Requirement - Design 3
          2. 8.2.3.2.2 Setting the Watchdog Window - Design 3
        3. 8.2.3.3 Application Curve - Design 3
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

at 1.6 V ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ ≤ +125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
MINTYPMAXUNIT
GENERAL
tINITCWD, CRST pin evaluation period(1)381µs
tSETTime required between changing SET0 and SET1 pins500µs
SET0, SET1 pin setup time1µs
Startup delay (3)300µs
DELAY FUNCTION
tRSTWatchdog reset delayCRST = NC170200230ms
CRST = 10 kΩ to VDD8.51011.5ms
WINDOW WATCHDOG FUNCTION
WD ratioWindow watchdog ratio of lower boundary to upper boundaryCWD = programmable, SET0 = 0, SET1 = 0(2)1/8
CWD = programmable, SET0 = 1, SET1 = 1(2)1/2
CWD = programmable, SET0 = 0, SET1 = 1(2)(4)3/4
tWDLWindow watchdog lower boundaryCWD = NC, SET0 = 0, SET1 = 019.122.525.9ms
CWD = NC, SET0 = 0, SET1 = 11.481.852.22ms
CWD = NC, SET0 = 1, SET1 = 0Watchdog disabled
CWD = NC, SET0 = 1, SET1 = 1680800920ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 07.659.010.35ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 17.659.010.35ms
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0Watchdog disabled
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 11.481.852.22ms
tWDUWindow watchdog upper boundaryCWD = NC, SET0 = 0, SET1 = 046.855.063.3ms
CWD = NC, SET0 = 0, SET1 = 123.37527.531.625ms
CWD = NC, SET0 = 1, SET1 = 0Watchdog disabled
CWD = NC, SET0 = 1, SET1 = 1136016001840ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 092.7109.0125.4ms
CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 1165.8195.0224.3ms
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0Watchdog disabled
CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 19.3511.012.65ms
tWD-setupSetup time required for device to respond to changes on WDI after being enabled150µs
Minimum WDI pulse duration50ns
tWD-delWDI to WDO delay50ns
(1) Refer to Section 8.1.2.2
(2) 0 refers to VSET ≤ VIL, 1 refers to VSET ≥ VIH.
(3) During power-on, VDD must be a minimum 1.6 V for at least 300 µs
(4) If this watchdog ratio is used, then tWDL(max) can overlap tWDU(min).