JAJSFU0A July   2018  – October 2021 TPS3430

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 Window Watchdog
        1. 7.3.2.1 SET0 and SET1
          1. 7.3.2.1.1 Enabling the Window Watchdog
          2. 7.3.2.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.2.1.3 SET0 and SET1 During Normal Watchdog Operation
      3. 7.3.3 Window Watchdog Timer
        1. 7.3.3.1 CWD
        2. 7.3.3.2 WDI Functionality
        3. 7.3.3.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 VDD is Above VPOR And Below VDD (min)( VPOR < VDD < VDD (min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Watchdog Reset Delay Timing
        2. 8.1.1.2 CRST Programmable Watchdog Reset Delay
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 CWD Adjustable Capacitor Watchdog Timeout
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Microcontroller with Watchdog Timer - Design 1
        1. 8.2.1.1 Design Requirements - Design 1
        2. 8.2.1.2 Detailed Design Procedure - Design 1
          1. 8.2.1.2.1 Meeting the Minimum Watchdog Reset Delay - Design 1
          2. 8.2.1.2.2 Setting the Watchdog Window - Design 1
          3. 8.2.1.2.3 Calculating the WDO Pull-up Resistor - Design 1
      2. 8.2.2 Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2
        1. 8.2.2.1 Design Requirements - Design 2
        2. 8.2.2.2 Detailed Design Procedure - Design 2
          1. 8.2.2.2.1 Meeting the Minimum Watchdog Reset Delay - Design 2
          2. 8.2.2.2.2 Setting the Watchdog Window - Design 2
          3. 8.2.2.2.3 Calculating the WDO Pull-up Resistor - Design 2
      3. 8.2.3 Monitoring Microcontroller with a Latching Window Watchdog Timer - Design 3
        1. 8.2.3.1 Design Requirements - Design 3
        2. 8.2.3.2 Detailed Design Procedure - Design 3
          1. 8.2.3.2.1 Meeting the Latching Output Requirement - Design 3
          2. 8.2.3.2.2 Setting the Watchdog Window - Design 3
        3. 8.2.3.3 Application Curve - Design 3
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8.1.2.2 CWD Adjustable Capacitor Watchdog Timeout

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to CWD, then a 375-nA constant-current source charges CCWD until VCWD = 1.21 V. The TPS3430 determines the window watchdog upper boundary with the formula given in Equation 4, where CCWD is in microfarads and tWDU is in seconds.

Equation 4. tWDU(typ) = 77.4 × CCWD + 0.055

The TPS3430 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that Equation 4 is for ideal capacitors, capacitor tolerances cause the actual device timing to vary. For the most accurate timing, use ceramic capacitors with COG dielectric material. As shown in Table 8-4, when using the minimum capacitor of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the watchdog upper boundary is 77.455 seconds. If a CCWD capacitor is used, Equation 4 can be used to set tWDU the window watchdog upper boundary. The window watchdog lower boundary is dependent on the SET0 and SET1 pins because these pins set the window watchdog ratio of the lower boundary to upper boundary; Table 8-5 shows how tWDU can be used to calculate tWDL based on the SET0 and SET1 pins.

Table 8-4 tWDU Values for Common Ideal Capacitor Values
CCWD WATCHDOG UPPER BOUNDARY (tWDU) UNIT
MIN (1) TYP MAX (1)
100 pF 56.77 62.74 68.7 ms
1 nF 119.82 132.4 144.98 ms
10 nF 750 829 908 ms
100 nF 7054 7795 8536 ms
1 µF 70096 77455 84814 ms
(1) Minimum and maximum values are calculated using ideal capacitors.
Table 8-5 Programmable CWD Timing
INPUT WATCHDOG LOWER BOUNDARY (tWDL) WATCHDOG UPPER BOUNDARY (tWDU) UNIT
CWD SET0 SET1 MIN TYP MAX MIN TYP MAX
CCWD 0 0 tWDU(min)x 0.125 tWDU x 0.125 tWDU(max) x 0.125 0.905 x tWDU(typ) tWDU(typ)(1) 1.095 x tWDU(typ) s
0 1 tWDU(min) x 0.75 tWDU x 0.75 tWDU(max) x 0.75 0.905 x tWDU(typ) tWDU(typ)(1) 1.095 x tWDU(typ) s
1 0 Watchdog disabled Watchdog disabled
1 1 tWDU(min) x 0.5 tWDU x 0.5 tWDU(max) x 0.5 0.905 x tWDU(typ) tWDU(typ)(1) 1.095 x tWDU(typ) s
(1) Calculated from Equation 4 using ideal capacitors.