JAJSFU8D November   2017  – June 2024 ADS8166 , ADS8167 , ADS8168

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Multiplexer
        1. 6.3.1.1 Multiplexer Configurations
        2. 6.3.1.2 Multiplexer With Minimum Crosstalk
        3. 6.3.1.3 Early Switching for Direct Sensor Interface
      2. 6.3.2 Reference
      3. 6.3.3 REFby2 Buffer
      4. 6.3.4 Converter Module
        1. 6.3.4.1 Internal Oscillator
        2. 6.3.4.2 ADC Transfer Function
      5. 6.3.5 Low-Dropout Regulator (LDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Channel Selection Using Internal Multiplexer
        1. 6.4.1.1 Manual Mode
        2. 6.4.1.2 On-The-Fly Mode
        3. 6.4.1.3 Auto Sequence Mode
        4. 6.4.1.4 Custom Channel Sequencing Mode
      2. 6.4.2 Digital Window Comparator
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Protocols
        1. 6.5.1.1 Enhanced-SPI Interface
          1. 6.5.1.1.1 Protocols for Configuring the Device
          2. 6.5.1.1.2 Protocols for Reading From the Device
            1. 6.5.1.1.2.1 SPI Protocols With a Single SDO
            2. 6.5.1.1.2.2 SPI Protocols With Dual SDO
            3. 6.5.1.1.2.3 Clock Re-Timer Data Transfer
              1. 6.5.1.1.2.3.1 Output Bus Width Options
      2. 6.5.2 Register Read/Write Operation
  8. 7 Register Maps
    1. 7.1 Interface and Hardware Configuration Registers
      1. 7.1.1 REG_ACCESS Register (address = 00h) [reset = 00h]
      2. 7.1.2 PD_CNTL Register (address = 04h) [reset = 00h]
      3. 7.1.3 SDI_CNTL Register (address = 008h) [reset = 00h]
      4. 7.1.4 SDO_CNTL1 Register (address = 0Ch) [reset = 00h]
      5. 7.1.5 SDO_CNTL2 Register (address = 0Dh) [reset = 00h]
      6. 7.1.6 SDO_CNTL3 Register (address = 0Eh) [reset = 00h]
      7. 7.1.7 SDO_CNTL4 Register (address = 0Fh) [reset = 00h]
      8. 7.1.8 DATA_CNTL Register (address = 10h) [reset = 00h]
      9. 7.1.9 PARITY_CNTL Register (address = 11h) [reset = 00h]
    2. 7.2 Device Calibration Registers
      1. 7.2.1 OFST_CAL Register (address = 18h) [reset = 00h]
      2. 7.2.2 REF_MRG1 Register (address = 19h) [reset = 00h]
      3. 7.2.3 REF_MRG2 Register (address = 1Ah) [reset = 00h]
      4. 7.2.4 REFby2_MRG Register (address = 1Bh) [reset = 00h]
    3. 7.3 Analog Input Configuration Registers
      1. 7.3.1 AIN_CFG Register (address = 24h) [reset = 00h]
      2. 7.3.2 COM_CFG Register (address = 27h) [reset = 00h]
    4. 7.4 Channel Sequence Configuration Registers Map
      1. 7.4.1 DEVICE_CFG Register (address = 1Ch) [reset = 00h]
      2. 7.4.2 CHANNEL_ID Register (address = 1Dh) [reset = 00h]
      3. 7.4.3 SEQ_START Register (address = 1Eh) [reset = 00h]
      4. 7.4.4 SEQ_ABORT Register (address = 1Fh) [reset = 00h]
      5. 7.4.5 ON_THE_FLY_CFG Register (address = 2Ah) [reset = 00h]
      6. 7.4.6 AUTO_SEQ_CFG1 Register (address = 80h) [reset = 00h]
      7. 7.4.7 AUTO_SEQ_CFG2 Register (address = 82h) [reset = 00h]
      8. 7.4.8 Custom Channel Sequencing Mode Registers
        1. 7.4.8.1 CCS_START_INDEX Register (address = 88h) [reset = 00h]
        2. 7.4.8.2 CCS_END_INDEX Register (address = 89h) [reset = 00h]
        3. 7.4.8.3 CCS_SEQ_LOOP Register (address = 8Ah) [reset = 00h]
        4. 7.4.8.4 CCS_CHID_INDEX_m Registers (address = 8C, 8E, 90, 92, 94, 96, 98, 9A, 9C, 9E, A0, A2, A4, A6, A8, and AAh) [reset = 00h]
        5. 7.4.8.5 REPEAT_INDEX_m Registers (address = 8D, 8F, 91, 93, 95, 97, 99, 9B, 9D, 9F, A1, A3, A5, A7, A9, and ABh) [reset = 00h]
    5. 7.5 Digital Window Comparator Configuration Registers Map
      1. 7.5.1  ALERT_CFG Register (address = 2Eh) [reset = 00h]
      2. 7.5.2  HI_TRIG_AINx[15:0] Register (address = 4Dh to 30h) [reset = 0000h]
      3. 7.5.3  LO_TRIG_AINx[15:0] Register (address = 71h to 54h) [reset = 0000h]
      4. 7.5.4  HYSTERESIS_AINx[7:0] Register (address = 4Fh to 33h) [reset = 00h]
      5. 7.5.5  ALERT_LO_STATUS Register (address = 78h) [reset = 00h]
      6. 7.5.6  ALERT_HI_STATUS Register (address = 79h) [reset = 00h]
      7. 7.5.7  ALERT_STATUS Register (address = 7Ah) [reset = 00h]
      8. 7.5.8  CURR_ALERT_LO_STATUS Register (address = 7Ch) [reset = 00h]
      9. 7.5.9  CURR_ALERT_HI_STATUS Register (address = 7Dh) [reset = 00h]
      10. 7.5.10 CURR_ALERT_STATUS Register (address = 7Eh) [reset = 00h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multiplexer Input Connection
    2. 8.2 Typical Applications
      1. 8.2.1 1MSPS DAQ Circuit With Lowest Distortion and Noise Performance
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3.     Power Supply Recommendations
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Analog Signal Path
        2. 8.3.1.2 Grounding and PCB Stack-Up
        3. 8.3.1.3 Decoupling of Power Supplies
        4. 8.3.1.4 Reference Decoupling
        5. 8.3.1.5 Reference Buffer Decoupling
        6. 8.3.1.6 Multiplexer Input Decoupling
        7. 8.3.1.7 ADC Input Decoupling
        8. 8.3.1.8 Example Schematic
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4.1.4 Custom Channel Sequencing Mode

In this mode the internal channel sequencer selectively scans channels from AIN0 through AIN7 in any order as defined by a user-programmable look-up table. Table 6-4 describes the configurability of this look-up table. Configure the device in custom channel sequencing mode by programming the SEQ_MODE[1:0] bits to 11b in the DEVICE_CFG register using a 3-byte register access. Table 6-4 shows that the channel scanning sequence is programmed by configuring the channel IDs in the register as space. A channel sample count is also programmed and associated with every channel ID. By default the channel sample count is 1, which means the sequence executes in the order of programmed channel IDs. If the channel sample count is greater than 1 then the corresponding channel is sampled and converted for a programmed number of times before switching to the next channel.

Table 6-4 Custom Channel Sequencing Configuration Space
REGISTER ADDRESS CHANNEL ID[2:0] REGISTER ADDRESS CHANNEL SAMPLE COUNT[7:0]
0x8C Index 0 : 3-bit channel ID (default = 0) 0x8D Index 0 : 8-bit sample count (default = 0xFF)
0x8E Index 1 : 3-bit channel ID (default = 0) 0x8F Index 1 : 8-bit sample count (default = 0xFF)
0x90 Index 2 : 3-bit channel ID (default = 0) 0x91 Index 2 : 8-bit sample count (default = 0xFF)
0x92 Index 3 : 3-bit channel ID (default = 0) 0x93 Index 3 : 8-bit sample count (default = 0xFF)
0x94 Index 4 : 3-bit channel ID (default = 0) 0x95 Index 4 : 8-bit sample count (default = 0xFF)
0x96 Index 5 : 3-bit channel ID (default = 0) 0x97 Index 5 : 8-bit sample count (default = 0xFF)
0x98 Index 6 : 3-bit channel ID (default = 0) 0x99 Index 6 : 8-bit sample count (default = 0xFF)
0x9A Index 7 : 3-bit channel ID (default = 0) 0x9B Index 7 : 8-bit sample count (default = 0xFF)
0x9C Index 8 : 3-bit channel ID (default = 0) 0x9D Index 8 : 8-bit sample count (default = 0xFF)
0x9E Index 9 : 3-bit channel ID (default = 0) 0x9F Index 9 : 8-bit sample count (default = 0xFF)
0xA0 Index 10 : 3-bit channel ID (default = 0) 0xA1 Index 10 : 8-bit sample count (default = 0xFF)
0xA2 Index 11 : 3-bit channel ID (default = 0) 0xA3 Index 11 : 8-bit sample count (default = 0xFF)
0xA4 Index 12 : 3-bit channel ID (default = 0) 0xA5 Index 12 : 8-bit sample count (default = 0xFF)
0xA6 Index 13 : 3-bit channel ID (default = 0) 0xA7 Index 13: 8-bit sample count (default = 0xFF)
0xA8 Index 14 : 3-bit channel ID (default = 0) 0xA9 Index 14 : 8-bit sample count (default = 0xFF)
0xAA Index 15: 3-bit channel ID (default = 0) 0xAB Index 15 : 8-bit sample count (default = 0xFF)

For application-specific scanning requirements, use start and stop pointers to define the channel scanning sequence. Program the start index in the CCS_START_INDEX register and the stop index in the CCS_END_INDEX register. Table 6-4 shows that the 4-bit index corresponds to the configuration index. The sequence starts executing from the index programmed in CCS_START_INDEX (default 0) and stop or loop-back from CCS_STOP_INDEX (default 15). The channel scanning sequence is looped-back to the start index from the stop index by setting the CCS_SEQ_LOOP register to 1b.

After configuring the channel scanning order, start index, and stop index, initiate the scanning by setting the SEQ_START bit to 1b. The ADC scans through the enabled channels after every CS rising edge as defined by the channel scanning order. When SEQ_START is set to 1b, the SDO-1/SEQSTS pin is pulled high until the last channel conversion frame is complete, as described in Figure 6-14. As illustrated in Figure 6-15, channel AIN0 is selected and SEQSTS/SDO-1 goes to Hi-Z after the last enabled channel conversion is complete.

As an example, Figure 6-15 provides a timing diagram for when the channel configuration is set as in Table 6-5. When AIN6 is converted, SEQSTS/SDO-1 goes to Hi-Z and AIN0 is selected as the active channel. If more conversion frames are launched at the end of the sequence, the device returns valid data corresponding to AIN0.

To use the device in easy capture mode follow these steps:

  • Set the SEQ_MODE[1:0] bits in the DEVICE_CFG register to 3.
  • Configure the channel sequence by setting registers 0x000C to 0x002B.
  • Configure the CCS_START_INDEX and the CCS_END_INDEX registers. In Figure 6-15, CCS_START_INDEX = 0 and CCS_STOP_INDEX = 1.
  • Configure the CCS_SEQ_LOOP register to 1 to indefinitely loop the sequence. In Figure 6-15, the CCS_SEQ_LOOP register = 0b.
  • Set the SEQ_START register to 1b to start executing the sequence.

Table 6-5 Custom Channel Sequencing Configuration Example
REGISTER ADDRESS CHANNEL ID[2:0] REGISTER ADDRESS CHANNEL SAMPLE COUNT[7:0]
0x8C 010b (channel 2) 0x8D 1
0x8E 110b (channel 6) 0x8F 1