JAJSFV9D September   2015  – July 2018 CC1310

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RSM Package
    2. 4.2 Signal Descriptions – RSM Package
    3. 4.3 Pin Diagram – RHB Package
    4. 4.4 Signal Descriptions – RHB Package
    5. 4.5 Pin Diagram – RGZ Package
    6. 4.6 Signal Descriptions – RGZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  RF Characteristics
    6. 5.6  Receive (RX) Parameters, 861 MHz to 1054 MHz
    7. 5.7  Receive (RX) Parameters, 431 MHz to 527 MHz
    8. 5.8  Transmit (TX) Parameters, 861 MHz to 1054 MHz
    9. 5.9  Transmit (TX) Parameters, 431 MHz to 527 MHz
    10. 5.10 PLL Parameters
    11. 5.11 ADC Characteristics
    12. 5.12 Temperature Sensor
    13. 5.13 Battery Monitor
    14. 5.14 Continuous Time Comparator
    15. 5.15 Low-Power Clocked Comparator
    16. 5.16 Programmable Current Source
    17. 5.17 DC Characteristics
    18. 5.18 Thermal Characteristics
    19. 5.19 Timing and Switching Characteristics
      1. 5.19.1 Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.19.2 Wakeup Timing
        1. Table 5-2 Wakeup Timing
      3. 5.19.3 Clock Specifications
        1. Table 5-3 24-MHz Crystal Oscillator (XOSC_HF)
        2. Table 5-4 32.768-kHz Crystal Oscillator (XOSC_LF)
        3. Table 5-5 48-MHz RC Oscillator (RCOSC_HF)
        4. Table 5-6 32-kHz RC Oscillator (RCOSC_LF)
      4. 5.19.4 Flash Memory Characteristics
        1. Table 5-7 Flash Memory Characteristics
      5. 5.19.5 Synchronous Serial Interface (SSI) Characteristics
        1. Table 5-8 Synchronous Serial Interface (SSI) Characteristics
    20. 5.20 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Main CPU
    3. 6.3  RF Core
    4. 6.4  Sensor Controller
    5. 6.5  Memory
    6. 6.6  Debug
    7. 6.7  Power Management
    8. 6.8  Clock Systems
    9. 6.9  General Peripherals and Modules
    10. 6.10 Voltage Supply Domains
    11. 6.11 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  デバイスの項目表記
    2. 8.2  ツールとソフトウェア
    3. 8.3  ドキュメントのサポート
    4. 8.4  テキサス・インスツルメンツのローパワーRF Webサイト
    5. 8.5  追加情報
    6. 8.6  コミュニティ・リソース
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

4.4 Signal Descriptions – RHB Package

Table 4-2 Signal Descriptions – RHB Package

PIN TYPE DESCRIPTION
NAME NO.
DCDC_SW 17 Power Output from internal DC/DC(1)
DCOUPL 12 Power 1.27-V regulated digital-supply decoupling(2)
DIO_0 6 Digital I/O GPIO, Sensor Controller
DIO_1 7 Digital I/O GPIO, Sensor Controller
DIO_2 8 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_3 9 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_4 10 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_5 15 Digital I/O GPIO, high-drive capability, JTAG_TDO
DIO_6 16 Digital I/O GPIO, high-drive capability, JTAG_TDI
DIO_7 20 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_8 21 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_9 22 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_10 23 Digital or analog I/O GPIO, Sensor Controller, Analog
DIO_11 24 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_12 25 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_13 26 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_14 27 Digital or analog I/O GPIO, Sensor Controller, analog
EGP – Power Ground; exposed ground pad
JTAG_TMSC 13 Digital I/O JTAG TMSC, high-drive capability
JTAG_TCKC 14 Digital I/O JTAG TCKC(3)
RESET_N 19 Digital input Reset, active low. No internal pullup.
RF_N 2 RF I/O Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P 1 RF I/O Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RX_TX 3 RF I/O Optional bias pin for the RF LNA
VDDR 29 Power 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4)
VDDR_RF 32 Power 1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5)
VDDS 28 Power 1.8-V to 3.8-V main chip supply(1)
VDDS2 11 Power 1.8-V to 3.8-V GPIO supply(1)
VDDS_DCDC 18 Power 1.8-V to 3.8-V DC/DC supply
X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1
X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2
X32K_Q1 4 Analog I/O 32-kHz crystal oscillator pin 1
X32K_Q2 5 Analog I/O 32-kHz crystal oscillator pin 2
(1) For more details, see the technical reference manual listed in Section 8.3.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™ Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.